在此篇論文中，提出並模擬一種嵌壁式通道架構應用於摻雜析離式蕭特基能障金氧半場效電晶體上，其能有效地抑制短通道效應現象，並能同時提供一個好的開閉電流比值，其中摻雜析離層的引入能獲取較大的開閉電流比值，有效的消除嵌壁式通道之架構所伴隨而來的寄生問題。此外，模擬結果顯示，嵌壁式通道之架構能對所分段之通道進行個別的操作行為，此一獨特的設計可以抑制汲極電壓作用在源極端之影響力，使得嵌壁式通道之電晶體在環境參數的變動下對於元件尺寸的變動較不敏感。然而嵌壁式通道架構本質上具有較差的導通電流尺寸，因此，提出一種改良式的嵌壁式通道架構，亦即使用非對稱性之架構來提供更好之導通電流，並降低了雙向導通的現象，最重要的是相較傳統摻雜析離式蕭特基能障電晶體而言，此改良之嵌壁式通道架構能同時保有其對隨閘極特徵長度降低而產生的短通道效應現象的抑制能力，這些元件特性使得嵌壁式通道之架構在未來元件電路應用上得以提供一個具有潛力的考量。

In this thesis, a recessed channel structure of dopant segregated Schottky barrier MOSFET (RC-DSSBMOS) is proposed and simulated for achieving suppressed short-channel effect and good on/off current ratio in scaled Schottky barrier MOSFETs. The simulated results shows that the recessed channel structure can alleviate the lateral field penetration effect coming from the source and drain electrodes. Thus, it is rather insensitive of short-channel device characteristics to the variations of drain voltages. The dopant segregation layer helps to have a larger on/off current ratio, and to counteract the parasitic problem caused by the recessed channel structure. Importantly, an asymmetric structure of RC-DSSBMOS is proposed and designed herein to have an enhanced driving on-current, minimized ambipolar conduction and a suitable short-channel effect as the devices are scaled down.

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