本篇論文主要在討論低密度查核奇偶碼 (Low density parity check code)。 從九十年代起，由於渦輪碼的發明讓人們對於迴旋解碼的特性產生了興趣，因此，同樣利用此解碼的 LDPC codes 也被重新發掘出來。從任意架構或有特定架構的組成中，我們討論此編碼對於錯誤率以及編碼長度之間的關係 。 一般而言，我們所關心的編碼長度是介於一千到一萬之間，此種編碼長度比較適合實際需求。另外，解碼過程中採用迴授式 Sum-product 法所造成的的收斂效果也將被討論。由於整個解碼過程可以用圖形化來表示，對於研究以及模擬有極大的幫助。
接著，我們會進行編碼器和解碼器的硬體模擬，這裡採用的是 -rotation LDPC code編碼，利用此編碼的數學特性，可以成功建構符合規格的 LDPC code外，並可利用數學式之間的關係勾勒出編碼器的架構圖。至於解碼器的部分，將會比較舊式與新式的解碼架構的優劣之處，新型解碼的方法利用簡化後的解碼邏輯，降低了解碼的複雜性，並增進了解碼速度。本身帶有平行解碼特性的 LDPC 碼也增加了解碼的效益。
最後，我們把此編碼加入多模光纖系統傳輸中，在新一代的光纖傳輸中，改善多模光纖的模與模之間的干擾已經被廣泛的討論，諸如新一代的光源設備，因應而生的新型入射方式，以及補償光纖通道所必須的等化器使用，目前的研究大多集中在如何將多模光纖的速度達到 10 Gb/s ， 我們也試著朝這目標前進，結合這些方法並討論最後的模擬結果。

In this paper low-density parity-check (LDPC) codes are investigated. The performance of these randomly and deterministically constructed codes in terms of the bit error rate is compared, where the block lengths of interest are between 1000 and 10000. These block lengths are suitable for practical applications. The convergence behavior of the decoding process using the iterative sum-product algorithm is analyzed for these finite length LDPC codes. The decoding process is visualized by animations of the evolution of the messages passed in the decoder. With these visualizations, successful decoding as well as decoding errors are investigated.
Then it will be discussed in implementing the graph encoder and decoder for low density parity check codes into an hardware component. Advanced decoding signal processing algorithms and systems architectures which enable low complexity and fast decoding solutions will be developed. For an efficient and fast implementation methodology, a fully parallel decoder architecture is proposed which is expected to enhance the throughput of the overall system dramatically.
Finally, I try to combine the LDPC codes with the multimode fiber transmission system, and analyze the associated performance result.

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