在本文中, 我們提出一個完整而且精確的可解析寫入模型, 此模型用以評估分離閘極快閃記憶體的全暫態寫入行為, 並首次結合動態汲極耦合參數, 無論用於定值波二元儲存或斜值波多元儲存. 經由準二維分析, 從偏壓相關及時域變動汲極電容耦合參數的可解析解開始, 以定電子電位障近似及最佳機率電子模型為基礎, 可解析寫入模型所導出之可解析解, 精確而且完整的預測全動態寫入行為, 並表達為物理, 外施電壓, 及外觀幾何的簡易函數, 並被用以發展於製作操作電壓操作時間之元件設計全功能圖. 與儲存電荷無關之本質電容耦合參數被用以作為元件設計之價值指標參數. 此外, 二元儲存或多元儲存陣列之讀出電流分佈的變異量的解析評估也被提出. 本文源級射入元件的再導向平均自由路徑的萃取值比通道熱電子元件的相對應值小了一個等級, 此呼應了源級射入元件約千分之二的高電子注入效率的物理直觀推測. 汲極耦合, 源級射入, 分離閘極快閃記憶體使用於多元儲存的可行性, 無論在理論上或實驗上, 也在本文中被驗證. 藉由本解析寫入模型可推得多元寫入的速度及準確度的設計準則. 可重覆讀寫之範圍微縮的機制也被詳細討論, 經由本可解析寫入模型的推導論證, 新的漸升波值寫入法也被提出可明顯改進元件的容忍度表現.

In this work, we present a comprehensive and accurate analytical model for evaluating the full transient programming behaviors of the drain-coupling split gate flash with dynamic drain coupling ratio for the first time either on the constant pulse for binary storages or on the staircase pulse for multilevel applications. Starting with the quasi-2D analysis on the bias-dependent and time-varying drain coupling ratio, our programming model based on the constant barrier height approximation and Lucky-Electron Model (LEM) is developed to simulate the complete operation plot of the time to program versus the programming voltage with various programming targets and technology parameters. The intrinsic coupling ratio independent of the storage charge is presented as the key figure of merit for the design index of the device. Besides, the analytical predictions of the variance of the read current distribution for binary and multilevel memory array are also presented. The extracted re-direction mean free path of our Source-Side Injection (SSI) device is smaller than that of Channel Hot-Electron (CHE) device by one order of magnitude provides the physical intuition of the derived high injection efficiency around 2/1000 for our SSI device. The feasibility for the multilevel SSI drain-coupling flash is theoretically and experimentally demonstrated. The design guidelines of program speed and program accuracy for multilevel programming are brought out by our analytical programming model. The mechanisms of cycling window closure are also discussed and new ramped-programming pulse method is proposed to improve the endurance performance significantly.

REFERENCES

CHAPTER 1

[1] G. Crisenza, R. Annunziata, E. Camerlenghi and P. Cappelletti, “Nonvolatile memories: issues, challenges and trends for the 2000’s scenario” Proc. ESSERC ‘96, Bologna, (Italy), pp. 121–130, 1996.
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[27] A. Modelli, A. Manstretta and G. Torelli “Basic feasibility constraints for multilevel CHE-programmed flash memories” IEEE Trans. Electron Devices, vol. 48, pp. 2032-2042, Dec. 2001.
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CHAPTER 3

[1] P. Cappelletti, C. Golla, P. Olivo and E. Zanoni, FLASH MEMORIES, Chap. 9 “Flash memories: market, marketing and economic challenges” 1st ed. Kluwer Academic Publishers. 1999.
[2] A. T. Wu, T. Y. Chan, P.K. Ko and C. Hu, “A novel high-speed, 5-volt programming EPROM structure with source-side injection” in IEDM Tech. Dig., 1986. pp. 584–587.
[3] R. Bez, D. Cantarelli, and S. Serra, “The channel hot electron programming of a floating gate MOSFET: an analytical study” 12th Nonvolatile Semi. Memory Worshop, Monterey, California (USA), 1992.
[4] H. Guan, D. Lee and G. P. Li, “An analytical model for optimization of programming efficiency and uniformity of split gate source-side injection superflash memory” IEEE Trans. Electron Devices, vol. 50, pp. 809–815, Mar. 2003.
[5] J. V. Houdt, L. Haspeslagh, D. Wellekens, L. Deferm, G. Groeseneken and H. E. Maes, “HIMOS-A high efficiency flash EEPROM cell for embedded memory applications” IEEE Trans. Electron Devices, vol. 40, pp. 2255–2263, Dec. 1993.
[6] B. J. Ahn, J. H. Sone, J. W. Kim, I. H. Choi and D. H. Kim, “A simple and efficient self-limiting erase scheme for high performance split-gate flash memory cells” IEEE Electron Devices Lett., vol. EDL-19, pp. 438–440, Nov. 1998.
[7] W. D. Brown and J. E. Brewer, Nonvolatile Semiconductor Memory Technology, Chap. 3 “Floating gate nonplanar devices” 1st ed. IEEE PRESS. 1987.
[8] http://www.tsmc.com.tw/english/technology/t0105.htm, “Embedded Non-Volatile Memory, TSMC's EmbFlash™”
[9] R. Mih, J. Harrington, K. Houlihan, H. K. Lee, K. Chan, J. Johnson, B. Chen, J. Yan, A. Schmidt, K. Kim, D. Shum, D. Lee, A. Levi and C. Lam, “0.18um modular triple self-aligned embedded split-gate flash memory” in 2000 Symp. VLSI Technology Dig. Tech. Papers, vol. 13.1, pp. 120-121.
[10] G. B. Jackson, S. V. Awsare, L. D. Engh, P. Holzmann, O. C. Kao, C. R. palmer, A. Raini, C. M. Liu and A. V. Kordesch, “An analoge record, playback, and processing system on a chip for mobile communications devices” IEEE J. Solid-State Circuits, vol. 35, pp. 446-449, Mar. 2000.
[11] N. K. Zous, Y. J. Chen, C. Y. Chin, W. J. Tsai, T. C. Lu, M. S. Chen, W. P. Lu, Tahui Wang, Samuel C. Pan and C. Y. Lu, “An endurance evaluation method for flash EEPROM” IEEE Trans. Electron Devices, vol. 40, pp. 2255–2263, Dec. 2004.
[12] G. Crisenza, R. Annunziata, E. Camerlenghi and P. Cappelletti, “Nonvolatile memories: issues, challenges and trends for the 2000’s scenario” Proc. ESSERC ‘96, Bologna, (Italy), pp. 121–130, 1996.
[13] L. Larcher, P. Pavan, L. Albani and T. Ghilardi, “Bias and W/L dependence of capacitive coupling coefficients in floating gate memory cells” IEEE Trans. Electron Devices, vol. 48, pp. 2081-2089, Dec. 2001.
[14] H. Fujiwara, M. Arimoto, T. Hkaida, S. Sudo, K. Kurooka, H. nagassawa, T. Hiroshima and K. Mamero, “A new method for measuring the coupling coefficient of a split-gate flash EEPROM” Proc. IEEE Int. Conf. On Microelectronic Test Structures, vol. 14, pp. 43-46, Mar. 2001.
[15] SST Data Book Flash Memory, 1997.
[16] C. M. Liu, J. Brennan, Jr., K. Chan, P. Guo, A. V. Kordesch and K. Y. Su, “On the capacitance coupling ratios of a source-side injection flash memory cell” Jap. J. Appl. Phys., vol. 40, pp. 2958-2962, Apr. 2001.
[17] Amy H. F. Chou, Y. Y. Yao, W. Z. Wong, C. S. Yang, Y. C. King and Charles C. H. Hsu, “New coupling ratio extraction method for split gate flash memory” 16th Nonvolatile Semi. Memory Worshop, Monterey, California (USA), 2000.
[18] S. Kianian, A. Levi, D. Lee and Y. W. Hu, “A novel 3 volts-only, small sector erase, high density flash EEPROM” in 1994 Symp. VLSI Technology Dig. Tech. Papers, pp. 71-72.
[19] A. A. M. Amin, “Speed optimized array architecture for flash EEPROMs” IEE Proc. G, vol. 140, pp. 177–181, Jun. 1993.
[20] H. S. Wong, “Gate current injection in MOSFET’s with a split-gate (virtual drain) structure” IEEE Electron Devices Lett., vol. EDL-14, pp. 262–264, May 1993.
[21] P. K. Ko, “Hot-electron effect in MOSFET” Ph. D. dissertation, Univ. California, Berkeley,1982.
[22] S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley. 1981.
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[26] T. Y. Chan, P. K. Ko and C. Hu, “A simple method to characterize substrate current in MOSFET’s” IEEE Electron Devices Lett., vol. EDL-5, pp. 505-507, Dec. 1984.
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[31] Z. H. Liu, C. Hu, J. H. Huang, T. Y. Chan, M. C. Jeng, P. K. Ko and Y. C. Cheng, “Threshold voltage model for deep-submicrometer MOSFET’s ” IEEE Trans. Electron Devices, vol. 40, pp. 86-94, Jan. 1993.
[32] K. Mayaram, J. C. Lee and C. Hu, “A model for the electric field in lightly doped drain structures” IEEE Trans. Electron Devices, vol. 34, pp. 1509-1518, July 1987.
[33] S. Tam, P. K. Ko and C. Hu, “Lucky-electron model of channel hot-electron injection in MOSFET’s” IEEE Trans. Electron Devices, vol. 31, pp. 1116–1125, Sep. 1984.
[34] S. Tam, P. K. Ko, C. Hu and R. S. Muller “Correlation between substrate and gate currents in MOSFET’s” IEEE Trans. Electron Devices, vol. 29, pp. 1740-1744, Nov. 1982.
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[36] T. H. Ning, C. M. Osburn, and H. N. Yu, “Emission probability of hot electrons from silicon into silicon dioxides” J. Appl. Phys., vol. 48, pp. 286–293, Jan. 1977.

CHAPTER 4

[1] A. T. Wu, T. Y. Chan, P.K. Ko and C. Hu, “A novel high-speed, 5-volt programming EPROM structure with source-side injection” in IEDM Tech. Dig., 1986. pp. 584–587.
[2] J. V. Houdt, P. Heremans, L. Deferm, G. Groeseneken and H. E. Maes, “Analysis of the Enhanced Hot-Electron Injection in Split-Gate Transistors Useful for EEPROM Applications” IEEE Trans. Electron Devices, vol. 39, pp. 1150–1156, May 1992.
[3] H. Guan, D. Lee and G. P. Li, “An analytical model for optimization of programming efficiency and uniformity of split gate source-side injection superflash memory” IEEE Trans. Electron Devices, vol. 50, pp. 809–815, Mar. 2003.
[4] C. M. Liu, J. Brennan, Jr., K. Chan, P. Guo, A. V. Kordesch and K. Y. Su, “On the capacitance coupling ratios of a source-side injection flash memory cell” Jap. J. Appl. Phys., vol. 40, pp. 2958-2962, Apr. 2001.
[5] S. Kianian, A. Levi, D. Lee and Y. W. Hu, “A novel 3 volts-only, small sector erase, high density flash EEPROM” in 1994 Symp. VLSI Technology Dig. Tech. Papers, pp. 71-72.
[6] W. D. Brown and J. E. Brewer, Nonvolatile Semiconductor Memory Technology, Chap. 3 “Floating gate nonplanar devices” 1st ed. IEEE PRESS. 1987.
[7] http://www.tsmc.com.tw/english/technology/t0105.htm, “Embedded Non-Volatile Memory, TSMC's EmbFlash™”
[8] R. Mih, J. Harrington, K. Houlihan, H. K. Lee, K. Chan, J. Johnson, B. Chen, J. Yan, A. Schmidt, K. Kim, D. Shum, D. Lee, A. Levi and C. Lam, “0.18um modular triple self-aligned embedded split-gate flash memory” in 2000 Symp. VLSI Technology Dig. Tech. Papers, vol. 13.1, pp. 120-121.
[9] G. B. Jackson, S. V. Awsare, L. D. Engh, P. Holzmann, O. C. Kao, C. R. palmer, A. Raini, C. M. Liu and A. V. Kordesch, “An analoge record, playback, and processing system on a chip for mobile communications devices” IEEE J. Solid-State Circuits, vol. 35, pp. 446-449, Mar. 2000.
[10] J. V. Houdt, G. Groeseneken and H. E. Maes, “An analytical model for the optimization of source-side injection flash EEPROM devices” IEEE Trans. Electron Devices, vol. 42, pp. 1314–1320, July 1995.
[11] H. S. Wong, “Gate current injection in MOSFET’s with a split-gate (virtual drain) structure” IEEE Electron Devices Lett., vol. EDL-14, pp. 262–264, May 1993.
[12] R. Bez, E. Camerlenghi, D. Cantarelli, L. Ravazzi and G. Crisenza “A novel method for the experimental determination of the coupling ratios in submicron EPROM and flash EEPROM cells” in IEDM Tech. Dig., 1990. pp. 99-102.
[13] J. V. Houdt, L. Haspeslagh, D. Wellekens, L. Deferm, G. Groeseneken and H. E. Maes, “HIMOS-A high efficiency flash EEPROM cell for embedded memory applications” IEEE Trans. Electron Devices, vol. 40, pp. 2255–2263, Dec. 1993.
[14] SST Data Book Flash Memory, 1997.
[15] H. Fujiwara, M. Arimoto, T. Hkaida, S. Sudo, K. Kurooka, H. nagassawa, T. Hiroshima and K. Mamero, “A new method for measuring the coupling coefficient of a split-gate flash EEPROM” Proc. IEEE Int. Conf. On Microelectronic Test Structures, vol. 14, pp. 43-46, Mar. 2001.
[16] P. K. Ko, “Hot-electron effect in MOSFET” Ph. D. dissertation, Univ. California, Berkeley,1982.
[17] K. Mayaram, J. C. Lee and C. Hu, “A model for the electric field in lightly doped drain structures” IEEE Trans. Electron Devices, vol. 34, pp. 1509-1518, July 1987.
[18] A. A. M. Amin, “Speed optimized array architecture for flash EEPROMs” IEE Proc. G, vol. 140, pp. 177–181, Jun. 1993.
[19] S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley. 1981.
[20] Y. H. Wang and M. C. Wu, “On the dynamic coupling ratio of drain-coupling source-side injection split gate flash using quasi-two dimensional analysis ” IEE Circiuts, Devices and Systems, accepted.
[21] T. Y. Chan, P. K. Ko and C. Hu, “A simple method to characterize substrate current in MOSFET’s” IEEE Electron Devices Lett., vol. EDL-5, pp. 505-507, Dec. 1984.
[22] S. Tam, P. K. Ko and C. Hu, “Lucky-electron model of channel hot-electron injection in MOSFET’s” IEEE Trans. Electron Devices, vol. 31, pp. 1116–1125, Sep. 1984.
[23] T. H. Ning, C. M. Osburn, and H. N. Yu, “Emission probability of hot electrons from silicon into silicon dioxides” J. Appl. Phys., vol. 48, pp. 286–293, Jan. 1977.
[24] N. Goldsman, L. Henrickson and J. Frey, “Reconciliation of a hot-electron
distribution function with the lucky electron-exponential model in Silicon” IEEE Electron Devices Lett., vol. EDL-11, pp. 472-474, Oct. 1990.
[25] J. V. Houdt, D. Wellekens, L. Faraone, L. Haspeslagh, L. Deferm, G. Groeseneken and H. E. Maes, “A 5 V-compatible flash EEPROM cell with microsecond programming time for embedded memory applications” IEEE Trans. Component, Package and Manufacturing Tech., vol. 17, pp. 380-389, Sep. 1994.
[26] A. Modelli, A. Manstretta and G. Torelli “Basic feasibility constraints for multilevel CHE-programmed flash memories” IEEE Trans. Electron Devices, vol. 48, pp. 2032-2042, Dec. 2001.
[27] S. Muramatsu, T. Kubota, N. Nishio, H. Shirai, M. Matsuo, N. Kodama, M. Horokawa, S. Saito, K. Arai and T. Okazawa, “The solutions of over-erase problem controlling poly-Si grain size-modified scaling principles for flash memory” IEDM Tech. Dig., 1994. pp. 847.

CHAPTER 5

[1] B. Ricco, G. Torelli, M. Lanzoni, A. Manstretta, H. E. Maes, D. Montanaria and A. Modelli, “Nonvolatile multilevel memories for digital applications” Proc. of the IEEE, vol. 86, pp. 2399-2421, Dec. 1998.
[2] B. Eitan, R. Kazerounian and A.Roy, “Multilevel Flash cells and their Trade-offs” IEDM 1996 Tech. Dig., pp. 169-171.
[3] J. Frayer, W. Saiki, H. V. Tran, D. Lee, P. Klinger and C. S. Su, “A 78mm2 (0.18um) 3.3V 256Mb multi-level NOR split-gate flash memory for mass storage” Proc. 20th 2003 NVSM Workshop, pp.29-30,
[4] W. D. Brown and J. E. Brewer, Nonvolatile Semiconductor Memory Technology, Chap. 3 “Floating gate nonplanar devices” 1st ed. IEEE PRESS. 1987.
[5] S. Bhattacharya, K. Lai, K. Fox, P. Chan, E. Worley, U. Sharma, L. Hwang and G. P. Li, “Improved performance and reliability of split gate source-side injected flash memory cells” IEDM 1996 Tech. Dig., pp. 339-342.
[6] R. Mih, J. Harrington, K. Houlihan, H. K. Lee, K. Chan, J. Johnson, B. Chen, J. Yan, A. Schmidt, K. Kim, D. Shum, D. Lee, A. Levi and C. Lam, “0.18um modular triple self-aligned embedded split-gate flash memory” in 2000 Symp. VLSI Technology Dig. Tech. Papers, vol. 13.1, pp. 120-121.
[7] G. B. Jackson, S. V. Awsare, L. D. Engh, P. Holzmann, O. C. Kao, C. R. palmer, A. Raini, C. M. Liu and A. V. Kordesch, “An analoge record, playback, and processing system on a chip for mobile communications devices” IEEE J. Solid-State Circuits, vol. 35, pp. 446-449, Mar. 2000.
[8] A. Modelli, A. Manstretta and G. Torelli, “Basic feasibility constraints for multilevel CHE-programmed flash memories” IEEE Trans. Electron Devices, vol. 48, pp. 2032-2042, Dec. 2001.
[9] S. Tam, P. K. Ko and C. Hu, “Lucky-electron model of channel hot-electron injection in MOSFET’s” IEEE Trans. Electron Devices, vol. 31, pp. 1116–1125, Sep. 1984.
[10] Y. H. Wang and M. C. Wu, “On the dynamic coupling ratio of drain-coupling source-side injection split gate flash using quasi-two dimensional analysis ” IEE Circiuts, Devices and Systems, accepted.
[11] Y. H. Wang, M. C. Wu, C. J. Lin, W. T. Chu, Y. T. Lin and C. S. Wang, “An analytical programming model for the drain-coupling source-side injection split gate flash EEPROM ” IEEE Trans. Electron Devices, accepted.

CHAPTER 6

[1] C. M. Liu, J. Brennan, Jr., K. Chan, P. Guo, A. V. Kordesch and K. Y. Su, “On the capacitance coupling ratios of a source-side injection flash memory cell” Jap. J. Appl. Phys., vol. 40, pp. 2958-2962, Apr. 2001.
[2] S. Kianian, A. Levi, D. Lee and Y. W. Hu, “A novel 3 volts-only, small sector erase, high density flash EEPROM” in 1994 Symp. VLSI Technology Dig. Tech. Papers, pp. 71-72.
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