在過去的二十年當中，快閃記憶體已經在儲存性電子產品當中站穩了腳步，而NAND快閃記憶體更因其成本低因此而成為了大量資料儲存的最佳解決方案。

然而隨著半導體製程的進步，半導體元件尺寸越來越小，並且元件在頻繁的抹除與寫入的情況底下，耐用性、可靠度以及元件壽命都面臨了嚴峻的挑戰。

在寫入以及抹除的循環測試當中，會使得缺陷在通道氧化層上產生，這些缺陷發生在氧化層和矽晶體交介面處，並且間接轉化為相位雜訊對晶片的性能造成影響，上述的行為造成了電子的捕捉以及釋放，連帶改變了通道的電流，這便是隨機電報雜訊，兼且在晶片尺寸縮小時，雜訊訊號比的比例亦會跟著上升；使得電路設計更為困難，因此分析製程及實驗對於隨機電報雜訊的影響就很重要。

隨著元件的微縮，隨機電報雜訊的影響開始不能被忽視。本文將會就1X奈米的NAND快閃記憶體去做測試，探討在什麼情況下，最容易觀察到隨機電報雜訊，並且就在產品製作過程當中所採用的不同製程對於隨機電報雜訊的影響來做討論。

In the past two decades, flash memory has played an important role in the storage market, and NAND flash memory has become the best solution for massive storage due to its low cost and high density.

However, as the medium CMOS technology progresses, the size of a memory cell becomes smaller and smaller, and the developers face with severe challenges in terms of memory durability, reliability, and device lifetime, when experience frequent erasing and programming during oper-ation.

In programming and erasing cycle tests, defects are created on the channel oxide film. These defects occur at the interface between the oxide layer and the substrate which converse to phase noise that affects the per-formance of memory array. The above behavior caused the capture and re-lease of electrons, which in turn changed the current of the channel, lead-ing to random telegraph noise. Also, as the chip size shrinks, signal to noise ratio decreases which cause additional challenges in readout circuit design much more difficult. Therefore, analysis on the influence of process and experiment on random telegraph noise is very important.

With the miniaturization of devices, the impact of random telegraph noise cannot be ignored. Therefore, this study employed 1X nanometer NAND flash memory as test subject, and discuss under the circumstances which one can induced random telegraph noise the most easily. Moreover, the effects of different manufacturing processes on RTN on 2D NAND flash memory arrays.
 

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