在本篇論文當中，我們提出了一個邏輯閘的模型。我們可以利用此模型來計算出此邏輯閘的輸出電壓波形以及供應電流波形。而當此邏輯閘受到製程變異的影響時，我們所提出來的模型，也可以把此製程變異的影響反應到模型上，進而將受到製程變異影響的程度反應在輸出電壓波形及供應電流波形上。而且我們的邏輯閘模型，也保留了其他邏輯閘所擁有的優點，例如多輸入變動（Multiple-input switching）以及非規律輸入波形等。
我們所提出的邏輯閘模型的複雜度及模擬速度，是介於傳統電流源模型（CSM）以及 HSPICE 模型之間。傳統的電流源模型由於結構過於簡單，所以無法準確的將製程變異的影響反應到邏輯閘模型當中; 而 HSPICE 模型雖然可以準確的反應製程變異的影響，但是由於模擬速度太慢的關係，而無法實際應用。而我們所提出的邏輯閘模型，就是希望能夠在準確度及模擬速度當中，找到一個平衡點。
我們的邏輯閘模型，主要是由數個電晶體模型所組成，而每一個電晶體模型，都是由電流源模型所構成。如此一來，雖然增加了模型的複雜度，但是解決了模型對於製程變異敏感度的問題，且模型的複雜度仍然小於 HSPICE 的模型。因此可以達到快而準的目標。
根據我們的實驗結果，當加入製程變異的影響時，我們的邏輯閘模型計算出的延遲誤差小於5%，平均的延遲誤差則小於 0.5% 。而且即使在多輸入變動，及非規律輸入波形的情況下，仍然能夠保持 5% 以下的延遲誤差。

In this thesis, we propose a cell delay model for accurately calculating cell delay and peak supply
current in the presence of process variations. In addition to cell delay and peak supply current,
the output voltage waveform for multiple-input switching (MIS) and non-ramped input can be also
derived with our model.
Our cell delay model is a current source model (CSM) and is designed to be more complex than
traditional CSM for handling the MIS problem and for enhancing the sensitivity to process variations.
The complexity and accuracy of our model lay midway between the conventional current
source model and the SPICE model. The conventional current source model is accurate and can
be fed in non-ramped input. However, it is less sensitive to variations, especially to the individual
variations of the transistors in logic cell. Although SPICE model can solve the process variation
issue, but the simulation time of SPICE model is too slow compared to that of CSM.
Our cell delay model is proposed for solving the issues above. The cell delay errors of our cell
delay model are lower than 5% in the presence of variations while the errors are lower than 3%
in the cases without process variations. The average cell delay errors are even lower than 0.5% in
the presence of process variations. However, the model that we propose is less complex than the
SPICE model. Besides, our cell delay model is also capable to deal with the non-ramped input and
multiple-input switching cases, as other CSM models can do.

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