在各種電路中，能源消耗分析扮演相當重要的角色。漏電流問題在先進奈米製程下變的越來越嚴重，也就是說，漏電流佔總能源消耗的比例一直呈現指數倍率成長。嚴重的漏電流將導致手持裝置待機時間縮短，增加使用者的不便。電源閘是減低漏電流最有效率的方法之一，另兩種方法分別為多種門檻電壓電晶體設計(Multi-Vth)以及體偏壓(body-bias)。在此篇論文中，我們鎖定電源閘方法，從時間的觀點切入，精確分析最大順時電流、電壓降以及睡眠電晶體系統之間的聯繫。進一步由此聯繫發展出一套睡眠電晶體面積最小化演算法，目的是在電源閘架構 - 分散式睡眠電晶體系統下，降低睡眠電晶體的總面積也就是寬度。傳統的方法都只考慮一個時脈內的瞬時最大電流來估計睡眠電晶體的面積。然而，透過我們在電源閘架構 - 分散式睡眠電晶體系統下由時間角度對瞬時最大電流進行分析後，我們發現傳統的方式往往過於悲觀而導致過大的睡眠電晶體面積。平均而言，與傳統的方式相比，我們的方法可以減低21%的睡眠電晶體面積以及漏電流消耗。我們更針對程式的計算複雜度進行改良，提出有效率的時脈分割方法。實驗結果顯示，平均而言，我們的時脈分割方法將比傳統的方法快了八倍。從各角度觀之，此論文的觀點是相當創新，而且實驗的結果是相當良好的。

Power gating is one of the most effective ways to reduce leakage power. In this paper, we introduce a new relationship among Maximum Instantaneous Current, IR drops and sleep transistor networks from a temporal viewpoint. Based on this relationship, we propose an algorithm to reduce the total sizes of sleep transistors in Distributed Sleep Transistor Network designs. On average, the proposed method can achieve 21% reduction in the sleep transistor size.

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