隨著製程技術的不斷進步，後段金屬連接線的尺寸也變得愈來愈小。因此，先前尚屬不需考慮的一些議題及困難將不停的浮現出來。其中之一就是在晶片中金屬連接線所產生的寄生效應，例如：寄生電容、寄生電阻以及寄生電感，這些效應在現在的電路中已逐漸變成是不可被忽略的。寄生電容會使得金屬連接線在傳遞訊號時花費比電晶體更多的時間，如此一來會導致我們對於整個晶片的效能難以準確評估。所以，必須建立出一個準確的金屬連接線電容模型，協助晶片設計者能更精確的評估出金屬連接線訊號延遲的時間。在現今的環境中要達成此一目標，較有效率的方式是透過電腦軟體產生出大量正確的測試結構檔案，然後再分析這些檔案執行後的結果。因此，我們必須隨著製程的進步，不斷地重新驗證這些軟體的準確性。

在這篇論文中，我們開發出一套軟體可以自動產生約八千個（共八種不同類型）測試結構輸入檔，並且使用產生出的測試檔對Clever和Raphael這兩種電磁場模擬軟體來進行驗證。雖然並沒有這些測試結構的實際電容數值，然而可以透過比對兩種軟體計算出的結果誤差，來檢驗所算出的數值是否合理。同時，也考量了製程變動以及光學效應等影響，因為這使得金屬連接線和via的形狀看起來分別像是梯型和圓錐形。所以，我們提出修改描述測試結構的方法，使得模擬的結構更接近真實的形狀。透過這樣更為詳細地描述，我們可以進一步驗證在先進製程下軟體的正確性和準確性。最後會分別針對這兩種軟體的準確度、執行時消耗的系統資源以及使用者環境介面做出討論，而這些結果將對晶片設計者在設計電路時有所幫助。

With the advancement of process technologies, the dimension of BEoL (Back End of the Production Line) interconnect has become smaller and smaller. Therefore, it will reveal many issues and challenges unceasingly that need to be concerned than before. One of them is on-chip interconnect induced issue, such as parasitic capacitance, parasitic resistance and parasitic inductance, they are attentive now. In the meanwhile, parasitic capacitance makes interconnect consume more time in transmitting signal than transistor, this situation results in an unexpected performance to the whole chip. Therefore, we need to model the interconnect capacitance accurately; then we can help IC designer to design their circuits and estimate the RC delay much precisely. Nowadays, the efficient way is to use computer software to massively generate correct test structures and collect the results to analyze them. Hence, these software need to be verify their accuracy when the process technologies make progress gradually.

In this paper, we develop a software package to generate more than 8 thousand (categorized into 8 types) test structure input files automatically and use them to verify two pieces of electromagnetic field simulation software, Clever and Raphael. Although we don’t have silicon data of these test structures, we can still compare the capacitance results simulated from Clever and Raphael to explain whether they are reasonable or not. Simultaneously, we consider the process variation and lithography effect, they cause the shape of interconnect and via look like a trapezoid and a cone respectively. Therefore, we modify the shape of our test structures much more close to realistic cases. By adopting this more comprehensive description as input files, we can examine the validity and accuracy of field simulation software. Finally, we discuss the accuracy, execution resources and user-friendly between Clever and Raphael to help IC designers to design their circuits.

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