現今人類的生活已經與半導體產品密不可分，而電晶體與記憶體元件為半導體產品中最基本的單元，當這些半導體元件的尺寸隨著摩爾定律的發展持續微縮，各式短通道效應及漏電現象成為棘手的問題。除此之外，傳統電晶體由於物理上的限制，其次臨界擺幅存在一極限值，使得其功耗將無法再進一步的提升；記憶體元件則面臨馮·紐曼架構的瓶頸，亦使得其效能受到大幅的限制。
本研究使用氧化鉿鋯作為閘極的氧化層，其鐵電性質產生的負電容效應可使電晶體的次臨界擺幅突破物理的極限，同樣以此材料製成的鐵電電晶體非揮發性記憶體，則有著比傳統記憶體更低的功耗與更高的操作速度，並可實現記憶體內的運算，突破馮·紐曼架構的框架。
本研究將分為兩個部分，透過電容匹配模型的理論，分別製作出應用於邏輯元件與記憶體元件的鐵電電晶體。
第一部分為鐵電氧化鉿鋯溝槽式鰭式電晶體。元件製作於絕緣層上覆矽基板，在鰭式通道及主動區定義後，利用非等向性蝕刻形成溝槽結構，此溝槽式結構可提升閘極包覆通道面積，並同時形成抬升式源/汲極結構，進一步提升閘極控制能力、抑制漏電流。結合 5 nm 之氧化鉿鋯氧化層帶來的負電容現象，溝槽式鰭式鐵電電晶體的次臨界擺幅值最v小來到 35.4 mV/dec，其 ION/ IOFF比值也高達 107，對於汲極引致能障下降及閘極引致汲極漏電流都有著出色的抑制能力。接著透過 Sentaurus TCAD 對溝槽式鰭式鐵電電晶體的模擬，驗證溝槽式結構有著增強氧化層電場的能力，可進一步提升鐵電層的鐵電性質。
第二部分則為鰭式鐵電電晶體非揮發性記憶體。一樣製作於絕緣層上覆矽基板，在主動區蝕刻後，透過原子層沉積，1 nm 之氮氧化鋁及 15 nm 之氧化鉿鋯被沉積作為氧化層，其中氮氧化鋁作為介面層可優化氧化層與通道的介面品質，提升記憶窗口。鰭式鐵電電晶體非揮發性記憶體在 ± 5 V 直流正反掃量測時，獲得了最大來到 2.40 V 的記憶窗口；而透過脈衝量測，施加 ± 4.5 V、100 ns 的脈衝即可進行寫入/抹除之操，此方法量測之記憶窗口更達到了 2.92 V。其耐用度可達 106、耐久度可達 104 秒以上，並仍然保持極佳的特性。
鐵電電晶體不論是應用於邏輯元件或是非揮發性記憶體元件中，皆有著出色的表現及良好的可靠度，加上鐵電電晶體與現今 CMOS 製程相容的特性，使其在未來的半導體產業應用上具有極高的潛力。

Transistor and memory are two basic components of semiconductor product. With the size of these semiconductor devices continue to scale down following the development of Moore’s law, various kinds of short channel effects (SCEs) and leakage phenomena become challenging problems. Moreover, due to the physical nature of traditional MOSFET, there is a limit value to its subthreshold swing (SS), which hinders traditional MOSFET from further improving its performance. On the other hand, due to the von Neumann bottleneck, the performance of traditional memory also being greatly restricted.
In this research, HfZrO2 (HZO) was used as gate oxide. The ferroelectricity of HZO will induce negative capacitance effect (NCE), which allow transistor to break through the physical limitation of SS. Furthermore, the ferroelectric field effect transistor (FeFET) non-volatile memory demonstrate lower power consumption and higher operation speed than traditional non-volatile memory. It can also realize in-memory-computation, break through the von Neumann bottleneck.
This thesis will be separated into two parts. Through capacitance matching theory, two types of FeFET for logic and memory device application were fabricated, respectively.
In chapter 3, Ferroelectric HZO Trench FinFET (Trench Fe-FinFET) was fabricated. The devices were fabricated on Silicon on Insulator (SOI) wafer. After fin and active formation, anisotropic etching was used to form the trench structure. This trench structure can increase the gate coverage over channel, and form raised source/drain structure simultaneously, therefore improve the gate control ability and suppress various SCEs. With the NCE of 5 nm HZO layer, Trench Fe-FinFET achieves minimum SS = 35.4 mV/dec, with on-off current ratio exceeding 107. It also presents outstanding immunity to drain-induced barrier lowering and gate-induced drain leakage. Furthermore, Sentaurus TCAD was used to verify its characteristic. It has been revealed that the trench structure can enhance the electric field across oxide layer, which can increase the ferroelectricity inside ferroelectric layer.
In chapter 4, ferroelectric FinFET Non-volatile Memory (Fe-FinFET NVM) was fabricated. Also fabricated on SOI wafer, after active formation, 1 nm of AlON and then 15 nm of HZO were deposited by atomic layer deposition (ALD). This AlON interfacial layer can improve interface quality between channel and oxide layer, therefore enhance memory window (MW). The MW of Fe-FinFET NVM achieves 2.40 V by ± 5 V direct current (DC) sweeping. By pulse measurement, it has been revealed that pulse with pulse voltage = ± 4.5 V and pulse width = 100 ns is enough to conduct program and erase operation. The MW extracted from pulse measurement achieves 2.92 V. Its endurance exceeds 106 cycles and its retention exceeds 104 second without any significant degradation.
FeFET presents outstanding characteristic and great reliability performance, for both logic device and non-volatile memory application. In addition, FeFET is compatible with modern CMOS processing technology, making it highly potential in the future application of semiconductor industry.

第一章
[1-1] International Roadmap for Devices and Systems (IRDS™) 2021 Edition: https://irds.ieee.org/editions/2021
[1-2] D. Hisamoto, W.-C. Lee, J. Kedzierski, E. Anderson, H. Takeuchi, K. Asano, T.-J. King, J. Bokor, Chenming Hu, "A folded-channel MOSFET for deep-sub-tenth micron era," International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217), 1998, pp. 1032-1034, doi: 10.1109/IEDM.1998.746531.
[1-3] Bin Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King, J. Bokor, Chenming Hu, M.-R. Lin, and D. Kyser, "FinFET scaling to 10 nm gate length," Digest. International Electron Devices Meeting,, 2002, pp. 251-254, doi: 10.1109/IEDM.2002.1175825.
[1-4] J. Robertson, “High dielectric constant oxides,” The European Physical Journal Applied Physics, vol. 28, no. 3, pp. 265-291, 2004, doi: 10.1051/epjap:2004206.
[1-5] M. H. Park, T. Schenk, C. M. Fancher, E. D. Grimley, C. Zhou, C. Richter, J. M. LeBeau, J. L. Jones, T. Mikolajick, and U. Schroeder, “A comprehensive study on the structural evolution of HfO2 thin films doped with various dopants,” Journal of Materials Chemistry C, vol. 5, no. 19, pp. 4677-4690, 2017, doi: 10.1039/c7tc01200d.
[1-6] J. Müller, T. S. Böscke, U. Schröder, S. Mueller, D. Bräuhaus, U. Böttger, L. Frey, and T. Mikolajick, “Ferroelectricity in Simple Binary ZrO2 and HfO2,” Nano Letters, vol. 12, no. 8, pp. 4318-4323, 2012, doi: 10.1021/nl302049k.
[1-7] M.-S. Yeh, Y.-C. Wu, M.-H. Wu, Y.-R. Jhan, M.-H. Chung, and M.-F. Hung, “High Performance Ultra-Thin Body (2.4nm) Poly-Si Junctionless Thin Film Transistors with a Trench Structure,” 2019 IEEE International Electron Devices Meeting, 2014, pp. 26.6.1-26.6.4, doi: 10.1109/IEDM.2014.7047115.
[1-8] M.-S. Yeh, Y.-C. Wu, M.-H. Wu, M.-H. Chung, Y.-R. Jhan and M.-F. Hung, “Characterizing the Electrical Properties of a Novel Junctionless Poly-Si Ultrathin-Body Field-Effect Transistor Using a Trench Structure,” IEEE Electron Device Letters, vol. 36, no. 2, pp. 150-152, Feb. 2015, doi: 10.1109/LED.2014.2378785.
[1-9] Y. Nakahara, K. Takeuchi, T. Tatsumi, Y. Ochiai, S. Manako, S. Samukawa and A. Furukawa, “Ultra-shallow in-situ-doped raised source/drain structure for sub-tenth micron CMOS,” Symposium on VLSI Technology. Digest of Technical Papers, 1996, pp. 174-175, doi: 10.1109/VLSIT.1996.507841.
[1-10] R. A. Vega and T. K. Liu, “A Comparative Study of Dopant-Segregated Schottky and Raised Source/Drain Double-Gate MOSFETs," IEEE Transactions on Electron Devices, vol. 55, no. 10, pp. 2665-2677, Oct. 2008, doi: 10.1109/TED.2008.2003024.
[1-11] K. Cheng, A. Khakifirooz, P. Kulkarni, S. Kanakasabapathy, S. Schmitz, A. Reznicek, T. Adam, Y. Zhu, J. Li, J. Faltermeier, T. Furukawa, L. F. Edge, B. Haran, S.-C. Seo, P. Jamison, J. Holt, X. Li, R. Loesing, Z. Zhu, R. Johnson, A. Upham, T. Levin, M. Smalley, J. Herman, M. Di, J. Wang, D. Sadana, P. Kozlowski, H. Bu, B. Doris, and J. O’Neill, “Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain,” 2009 Symposium on VLSI Technology, 2009, pp. 212-213.
[1-12] M. Saitoh, Y. Nakabayashi, K. Uchida and T. Numata, “Short-Channel Performance Improvement by Raised Source/Drain Extensions With Thin Spacers in Trigate Silicon Nanowire MOSFETs,” IEEE Electron Device Letters, vol. 32, no. 3, pp. 273-275, March 2011, doi: 10.1109/LED.2010.2101043.
[1-13] J. Backus, “Can programming be liberated from the von Neumann style? a functional style and its algebra of programs,” Communications of ACM, Volume 21 Issue 8, 1978, pp 613–641, doi: 10.1145/359576.359579.
[1-14] S. Slesazeck, and T. Mikolajick, “Nanoscale resistive switching memory devices: a review,” Nanotechnology, Volume 30, Number 35, June 2019, doi: 10.1088/1361-6528/ab2084
[1-15] H. Amrouch, J.-J. Chen, K. Roy, Y. Xie, I. Chakraborty, W. Huangfu, L. Liang, F. Tu, C. Wang, and M. Yayla, “Brain-Inspired Computing: Adventure from Beyond MOS Technologies to Beyond von Neumann Architectures,” 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2021, pp. 1-9, doi: 10.1109/ICCAD51958.2021.9643488.
[1-16] S. Beyer et al., “FeFET: A versatile CMOS compatible device with game-changing potential,” 2020 IEEE International Memory Workshop (IMW), 2020, pp. 1-4, doi: 10.1109/IMW48823.2020.9108150.
[1-17] J.-H. Bae, D. Kwon, N. Jeon, S. Cheema, A.-J. Tan, C. Hu, and S. Salahuddin, “Highly Scaled, High Endurance, Ω-Gate, Nanowire Ferroelectric FET Memory Transistors,” IEEE Electron Device Letters, vol. 41, no. 11, pp. 1637-1640, Nov. 2020, doi: 10.1109/LED.2020.3028339.
[1-18] T. Mikolajick, S. Slesazeck, M.-H. Park, and U. Schroeder, “Ferroelectric hafnium oxide for ferroelectric random-access memories and ferroelectric field-effect transistors,” MRS Bulletin, vol. 43, no. 5, pp. 340-346, 2018, doi:10.1557/mrs.2018.92.
[1-19] H. Mulaosmanovic, S. Slesazeck, J. Ocker, M. Pesic, S. Müller, S. Flachowsky, J. Müller, P. Polakowski, J. Paul, S. Jansen, S. Kolodinski, C. Richter, S. Piontek, T. Schenk, A. Kersch, C. Künneth, R. van Bentum, U. Schröder, T. Mikolajick, “Evidence of single domain switching in hafnium oxide based FeFETs: Enabler for multi-level FeFET memory cells,” 2015 IEEE International Electron Devices Meeting (IEDM), 2015, pp. 26.8.1-26.8.3, doi: 10.1109/IEDM.2015.7409777.
[1-20] S. De, D. D. Lu, H.-H. Le, S. Mazumder, Y.-J. Lee, W.-C. Tseng, B.-H. Qiu, M. A. Baig, P.-J. Sung, C.-J. Su, C.-T. Wu, W.-F. Wu, W.-K. Yeh, Y.-H. Wang, “Ultra-Low Power Robust 3bit/cell Hf0.5Zr0.5O2 Ferroelectric FinFET with High Endurance for Advanced Computing-In-Memory Technology,” 2021 Symposium on VLSI Technology, 2021, pp. 1-2.
第二章
[2-1] Muhammad A. Alam, “ A Tutorial Introduction to Negative Capacitor Field Effect Transistors,” 2015/10/03, https://nanohub.org/resources/23157/about.
[2-2] A. I. Khan, K. Chatterjee, J. P. Duarte, Z. Lu, A. Sachid, S. Khandelwal, R. Ramesh, C. Hu, and S. Salahuddin, “Negative Capacitance in Short-Channel FinFETs Externally Connected to an Epitaxial Ferroelectric Capacitor,” IEEE Electron Device Letters, vol. 37, no. 1, pp. 111-114, Jan. 2016, doi: 10.1109/LED.2015.2501319.
[2-3] M. Si, C. Jiang, C. J. Su, Y. T. Tang, L. Yang, W. Chung, M. A. Alam, and P. D. Ye, “Sub-60 mV/dec Ferroelectric HZO MoS2 Negative Capacitance Field-effect Transistor with Internal Metal Gate: the Role of Parasitic Capacitance,” 2017 IEEE International Electron Devices Meeting (IEDM), 2017, pp. 23.5.1-23.5.4, doi: 10.1109/IEDM.2017.8268447.
[2-4] S. Salahuddin and S. Datta, “Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices,” Nano Letters, vol. 8, pp. 405-410, 2008, doi:10.1021/nl071804g.
[2-5] M. N. K. Alam, P. Roussel, M. Heyns, and J. V. Houdt, “Positive non-linear capacitance: the origin of the steep subthreshold-slope in ferroelectric FETs,” Scientific Reports, vol 9, no. 1, pp. 14957, Oct. 2019, doi: 10.1038/s41598-019-51237-2.
[2-6] H.-P. Lee, C.-L. Yu, W.-X. You and P. Su, “Investigation and comparison of design space for ultra-thin-body GeOI/SOI negative capacitance FETs,” 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2017, pp. 1-2, doi: 10.1109/VLSI-TSA.2017.7942460.
[2-7] C. Jiang, R. Liang and J. Xu, “Investigation of Negative Capacitance Gate-all-Around Tunnel FETs Combining Numerical Simulation and Analytical Modeling,” in IEEE Transactions on Nanotechnology, vol. 16, no. 1, pp. 58-67, Jan. 2017, doi: 10.1109/TNANO.2016.2627808.
[2-8] A. Saeidi, F. Jazaeri, F. Bellando, I. Stolichnov, G. V. Luong, Q.-T. Zhao, S. Mantl, C. C. Enz, and A. M. Ionescu, “Negative Capacitance as Performance Booster for Tunnel FETs and MOSFETs: An Experimental Study,” in IEEE Electron Device Letters, vol. 38, no. 10, pp. 1485-1488, Oct. 2017, doi: 10.1109/LED.2017.2734943.
[2-9] W. Cao, K. Banerjee, “Is negative capacitance FET a steep-slope logic switch?.” in Nature Communications, 11, 196, 2020, doi: 10.1038/s41467-019-13797-9.
[2-10] A. Saeidi, F. Jazaeri, F. Bellando, I. Stolichnov, C. C. Enz and A. M. Ionescu, “Negative capacitance field effect transistors; capacitance matching and non-hysteretic operation,” 2017 47th European Solid-State Device Research Conference (ESSDERC), 2017, pp. 78-81, doi: 10.1109/ESSDERC.2017.8066596.
[2-11] T. Yu, W. Lü, Z. Zhao, P. Si, and K. Zhang, “Effect of different capacitance matching on negative capacitance FDSOI transistors,” in Microelectronics Journal, volume 98, April 2020, 104730, doi: 10.1016/j.mejo.2020.104730.
[2-12] H. Agarwal, P. Kushwaha, Y.-K. Lin , M.-Y. Kao , Y.-H. Liao, A. Dasgupta , S. Salahuddin , and C. Hu, “Proposal for Capacitance Matching in Negative Capacitance Field-Effect Transistors,” in IEEE Electron Device Letters, vol. 40, no. 3, pp. 463-466, March 2019, doi: 10.1109/LED.2019.2891540.
[2-13] C. W. Yeung, A. I. Khan, S. Salahuddin and C. Hu, “Device design considerations for ultra-thin body non-hysteretic negative capacitance FETs,” 2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S), 2013, pp. 1-2, doi: 10.1109/E3S.2013.6705876.
[2-14] A. Kerber, E. Cartier, L. Pantisano, M. Rosmeulen, R. Degraeve, T. Kauerauf, G. Groeseneken, H.E. Maes, and U. Schwalke, “Characterization of the VT instability in SiO2 HfO2 gate dielectrics,” 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual., 2003, pp. 41-45, doi: 10.1109/RELPHY.2003.1197718.
[2-15] E. Yurchuk, S. Mueller, D. Martin, S. Slesazeck, U. Schroeder, T. Mikolajick, J. Müller, J. Paul, R. Hoffmann, J. Sundqvist, T. Schlösser, R. Boschke, R. van Bentum, and M. Trentzsch, “Origin of the endurance degradation in the novel HfO2-based 1T ferroelectric non-volatile memories,” 2014 IEEE International Reliability Physics Symposium, 2014, pp. 2E.5.1-2E.5.5, doi: 10.1109/IRPS.2014.6860603.
[2-16] E. Yurchuk, J. Müller, S. Müller, J. Paul, M. Pešic, R. van Bentum, U. Schroeder, and T. Mikolajick, “Charge-Trapping Phenomena in HfO2-Based FeFET-Type Nonvolatile Memories,” in IEEE Transactions on Electron Devices, vol. 63, no. 9, pp. 3501-3507, Sept. 2016, doi: 10.1109/TED.2016.2588439.
[2-17] K. Ni, P. Sharma, J. Zhang, M. Jerry, J. A. Smith, K. Tapily, R. Clark, S. Mahapatra, and S. Datta, “Critical Role of Interlayer in Hf0.5Zr0.5O2 Ferroelectric FET Nonvolatile Memory Performance,” in IEEE Transactions on Electron Devices, vol. 65, no.6, pp.2461- 2469, June 2018, doi: 10.1109/TED.2018.2829122.
[2-18] C. -Y. Chan, K. -Y. Chen, H. -K. Peng and Y. -H. Wu, “FeFET Memory Featuring Large Memory Window and Robust Endurance of Long-Pulse Cycling by Interface Engineering using High-k AlON,” 2020 IEEE Symposium on VLSI Technology, 2020, pp. 1-2, doi: 10.1109/VLSITechnology18217.2020.9265103.
[2-19] H.-K. Peng, C.-Y. Chan, K.-Y. Chen, and Y.-H. Wu, “Enabling large memory window and high reliability for FeFET memory by integrating AlON interfacial layer,” Applied Physics Letters, vol. 118, issue 10, pp. 103503, 2021, doi: 10.1063/5.0036824
[2-20] T. Ali, P. Polakowski, S. Riedel, T. Büttner, T. Kämpfe, M. Rudolph, B. Pätzold, K. Seidel, D. Löhr, R. Hoffmann, M. Czernohorsky, K. Kühnel, P. Steinke, J. Calvo, K. Zimmermann, and J. Müller, “High Endurance Ferroelectric Hafnium Oxide-Based FeFET Memory Without Retention Penalty,” in IEEE Transactions on Electron Devices, vol. 65, no. 9, pp. 3769-3774, Sept. 2018, doi: 10.1109/TED.2018.2856818.
[2-21] H. Mulaosmanovic, S. Dünkel, J. Müller, M. Trentzsch, S. Beyer, E. T. Breyer , T. Mikolajick ,and S. Slesazeck, “Impact of Read Operation on the Performance of HfO2-Based Ferroelectric FETs,” in IEEE Electron Device Letters, vol. 41, no. 9, pp. 1420-1423, Sept. 2020, doi: 10.1109/LED.2020.3007220.
第三章
[2-22] M. Hoffmann, U. Schroeder, T. Schenk, T. Shimizu, H. Funakubo, O. Sakata, D. Pohl, M. Drescher, C. Adelmann, R. Materlik, A. Kersch, and T. Mikolajick, “Stabilizing the ferroelectric phase in doped hafnium oxide,” Journal of Applied Physics, 118, 072006 (2015), doi: 10.1063/1.4927805
第四章
[4-1] H. Mulaosmanovic, J. Ocker, S. Müller, M. Noack, J. Müller, P. Polakowski, T. Mikolajick, and S. Slesazeck, “Novel ferroelectric FET based synapse for neuromorphic systems,” 2017 Symposium on VLSI Technology, 2017, pp. T176-T177, doi: 10.23919/VLSIT.2017.7998165.
[4-2] G. Indiveri and S. Liu, “Memory and Information Processing in Neuromorphic Systems,” in Proceedings of the IEEE, vol. 103, no. 8, pp. 1379-1397, Aug. 2015, doi: 10.1109/JPROC.2015.2444094.
[4-3] S.-C. Yan, G.-M. Lan, C.-J. Sun, Y.-H. Chen, C.-H. Wu, H.-K. Peng, Y.-H. Lin, Y.-H. Wu, and Y.-C. Wu, “High Speed and Large Memory Window Ferroelectric HfZrO₂ FinFET for High-Density Nonvolatile Memory,” in IEEE Electron Device Letters, vol. 42, no. 9, pp. 1307-1310, Sept. 2021, doi: 10.1109/LED.2021.3097777.
[4-4] H. Mulaosmanovic, E.-T. Breyer, T. Mikolajick and S. Slesazeck, “Ferroelectric FETs With 20-nm-Thick HfO2 Layer for Large Memory Window and High Performance,” in IEEE Transactions on Electron Devices, vol. 66, no. 9, pp. 3828-3833, Sept. 2019, doi: 10.1109/TED.2019.2930749.
[4-5] C.-Y. Liao, K.-Y. Hsiang, F.-C. Hsieh, S.-H. Chiang, S.-H. Chang, J.-H. Liu, C.-F. Lou, C.-Y. Lin, T.-C. Chen, C.-S. Chang, and M.-H. Lee, “Multibit Ferroelectric FET Based on Nonidentical Double HfZrO2 for High-Density Nonvolatile Memory,” in IEEE Electron Device Letters, vol. 42, no. 4, pp. 617-620, April 2021, doi: 10.1109/LED.2021.3060589.
[4-6] S. De, Sourav De, D. D. Lu, H.-H. Le, S. Mazumder, Y.-J. Lee, W.-C. Tseng, B.-H. Qiu, Md. A. Baig, P.-J. Sung, C.-J. Su, C.-T. Wu, W.-F. Wu, W.-K. Yeh, and Y.-H. Wang, “Ultra-Low Power Robust 3bit/cell Hf0.5Zr0.5O2 Ferroelectric FinFET with High Endurance for Advanced Computing-In-Memory Technology,” 2021 Symposium on VLSI Technology, 2021, pp. 1-2.
第五章
[5-1] M.–J. Tsai, P.-J. Chen, C.-C. Hsu, D.-B. Ruan, F.-J. Hou, P.-Y. Peng, Y.-C. Wu, “Atomic-Level Analysis of Sub-5-nm-Thick Hf0.5Zr0.5O2 and Characterization of Nearly Hysteresis-Free Ferroelectric FinFET,” in IEEE Electron Device Letters, vol. 40, no. 8, pp. 1233-1236, Aug. 2019, doi: 10.1109/LED.2019.2922239.