在電信系統中，語音傳輸是最重要也是最常見的服務項目。由於現實環境中的頻寬限制，許多用來減少傳輸負擔的語音壓縮標準也因此產生。為了同時考量經過壓縮後的語音品質與語音訊號的壓縮比率，開發者只能以非常複雜的演算法來實作語音壓縮標準。這樣一來，使得語音的編解碼的執行相當沒有效率。
對於傳統精簡指令集處理器，程式語言編譯器通常可以得到相當高效率的編譯效果。此外，傳統精簡指令集處理器在處理控制型態的程式也有相當好的表現。但在處理需要對資料做大量且重覆運算的多媒體應用程式方面，精簡指令集處理器卻不能帶給我們滿意的執行效能。
本篇論文提出了一個針對語音解碼處理的新精簡指令集架構。我們以這個新架構來改進精簡指令集處理器執行G.729解碼器的效能。為了建構這個新架構，我們開發了幾個新的硬體元件來完成我們的設計。這些硬體元件以可合成的Verilog HDL語法撰寫，而且也成功的以Synopsys Design Compiler與TSMC 0.35μm製程之標準函式庫進行邏輯合成。藉由將這些新硬體元件整合到傳統精簡指令集處理器架構中，我們成功地完成了一個能有效處理語音解碼過程的新精簡指令集架構。
根據實驗數據，比起傳統精簡指令集架構，新架構的執行效率可以達到約52%的改進幅度。我們相信，對一個需要同時兼顧控制型態應用程式與語音解碼處理的平台來說，我們所提出新架構是一個不需採用額外且昂貴的數位訊號處理器，並且兼具低成本與高效能的解決方案。

Speech communication is most essential and common service in telecommunication. Due to the limited bandwidth of the practical communication network, various speech compression standards are developed to alleviate the transmission overhead. In order to consider both the speech quality and the compression ratio, compression standards can only be implemented by employing very complex algorithms which make the performance of decoding processing inefficient.
Traditional RISC processors are compiler-friendly and highly efficient in handling control type of applications. However, in the case of executing multimedia applications (ex: video, audio, speech program) which need to execute huge amount of computations iteratively, we won’t obtain a satisfied performance by employing a RISC processor to deal with the multimedia applications.
This thesis proposes a new application-specific RISC architecture for speech decoding processing. The new architecture is designed to improve the performance of processing G.729 speech decoder. We develop some enhanced hardware components to build the new architecture. These components are implemented in synthesizable Verilog HDL and successfully synthesized by Synopsys Design Compiler as well as TSMC 0.35μm target library. By integrating these enhanced hardware components into the traditional RISC architecture, we successfully develop the new RISC architecture with the capability of efficient speech decoding processing.
According to our simulation result, we found that the application-specific RISC architecture can achieve about 52% performance improvement than the traditional RISC architecture. We believe that it is a lower-cost and efficient solution for the platform which needs to take care of control type of applications and speech decoding application simultaneously without employing an additional and costly DSP.

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