在元件閘極氧化層厚度快速縮小的趨勢下，氧化層厚度薄至25□以下時元件會因為直接穿遂效應而產生很大的閘極漏電流，因此，尋找高介電係數(High-K)閘極介電層以替代原先二氧化矽介電層，是當今非常重要的一個課題。然而在材料替換的過程中，許多問題產生，如電荷捕獲(charge trapping)，臨界電壓(threshold voltage)飄移，載子遷移率(mobility)下降等，因此應用在高介電係數閘極介電層電晶體的界面缺陷(interface traps)及氧化層缺陷(oxide traps)可靠度分析因應而生。本論文主要是觀察High-K介電層與矽基板之間的邊緣缺陷，其包含了界面缺陷和氧化層電荷。
第一部分是High-K介電層金氧半電晶體的界面缺陷密度分佈量測:我們採用了電荷汲引量測技術及高低頻轉導量測技術，藉由這兩種量測技術以觀察在能隙中不同能量的界面缺陷密度分佈，及以電荷分離方法比較，以做為元件的可靠度評估。
第二部份是High-K介電層金氧半電晶體的氧化層電荷縱向深度分佈量測:不同於以往的材料分析方式，我們採用了低頻閘極脈衝的電荷汲引量測技術，利用這樣的量測方式可以探得界面與氧化層中間不完美的鍵結，並且觀察氧化層電荷對臨界電壓的影響。

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