隨著製程的進步、單位元件尺寸的縮小，為了保證電路上的時序限制能夠被滿足，即時性測試被大量地運用在找出電路上的延遲缺陷。然而，在即時性測試的當下，電路會有極為可觀數量的元件同時發生轉換，使得電路上的供電開始不穩，產生所謂的電流電阻壓降效應。這會使電路的效能降低，甚至功能發生錯誤，使電路本身被誤判為錯誤。故我們需要設法降低在即時性測試中的元件轉換率。

　　為了解決前段所敘述的問題，X填值的方法經常為人所使用。在即時性測試的測試樣本中，有著高比例的X值，而這X值可以隨意地填入０或１。經由將X填入較好的值，新產生的測試樣本可以有效地降低元件的轉換率，以防止在即時性測試中，電路上產生嚴重的電流電阻壓降效應。

　　在這篇論文中，我們提出了兩個方法來幫助我們執行X填值的動作。分別是考慮電路裡各元件的實際位置以及向後傳遞來X值來決定填值。首先當在某一小區域內的元件大量地發生轉換，可以確定會產生很嚴重的電流電阻壓降效應。這時我們選出一些對於電流電阻壓降效應影響力很大的元件，使用向後傳遞X值的方法，以確保這些元件在X填值後可以有效降低這小區域內的元件轉換率。

In order to ensure that a circuit meets timing requirements, at-speed scan test is widely used to detect delay defects. However, at-speed scan test suffers
from the test-induced yield loss. Because the switching activity of whole circuit during test mode is much higher than that during normal mode, the large portion of gates simultaneously switching contributes to serious IR-drop
delay. Thus, propagation delay does not meet the timing constraint only at test mode. This IR-drop problem during test mode exacerbates delay defects and results in false failures. In this thesis, we take the X-‾lling approach to
reducing the IR-drop e□ect during at-speed test. The main difference between our approach and the previous X-filling methods lies in two aspects. The first one is that we take the spatial information into consideration in our approach. The second one is how X-filling is performed. In previous work [7, 8, 9], a forward-propagation approach is taken, while a backward-propagation approach is proposed in this thesis. Compared with the previous work [9], the experimental result shows that we have 26% reduction in the worst IR-drop and 28% reduction in the average IR-drop. The IR-drop reduction also improves the IR-drop delay. We have 2.4% additional IR-drop delay in the critical paths as compared with the optimal path delay without considering IR-drop effect, while the previous work [9] has 3.4% additional IR-drop delay in the critical paths.

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