隨著現今科技日新月異，在半導體產業快術發展下，人類生活和半導體產品密不可分。當半導體尺寸隨著摩爾定律微縮下，將面臨著許多問題，包括物理上的極限以及半導體製程技術上的困難，要克服這些問題成為了目前最重要的議題。從古至今，提出了許多改善短通道效應的方法，例如：改變閘極結構及材料、氧化層採用高介電係數材料、改變通道摻雜結構，像是無接面式電晶體等等，因此有許多學者正朝著這些方向研究，並發表了豐碩的成果，期望能為現今的科技做出貢獻。
本篇論文分別使用了超晶格氧化鉿鋯材料和氧化鉿鋯材料作為MFM電容的鐵電層以及環繞式閘極多晶矽無接面式鐵電電晶體的閘極氧化層，並且進行材料分析以及觀察特性，接著以超晶格氧化鉿鋯材料進一步製作了p型電晶體，並將n型及p型電晶體利用電路連接的方式，進行CMOS反相器的量測及分析。
在材料分析及電容量測的部分，透過GIXRD分析，確認兩種材料均具有鐵電特性，並發現超晶格氧化鉿鋯材料擁有較大的Orthorhombic/Tetragonal混和晶相，相較之下，氧化鉿鋯材料的Monoclinic晶相比例較高，顯示超晶格氧化鉿鋯材料具有較優越的鐵電特性。在電容的特性量測中，得知超晶格氧化鉿鋯電容的介電係數及殘餘極化量分別比氧化鉿鋯電容提高了13%及11%，超晶格氧化鉿鋯電容展現優於氧化鉿鋯電容的特性。
在電晶體的研究中，比較了分別使用超晶格氧化鉿鋯材料和氧化鉿鋯材料作為環繞式閘極多晶矽無接面式鐵電電晶體的閘極氧化層，並證實了超晶格氧化鉿鋯材料在電晶體中的優越性能，特別是其較小的次臨界擺幅、更高的ION/IOFF以及更低的DIBL。此外，我們製作了以超晶格氧化鉿鋯材料做為氧化層的n型極p型電晶體，並成功進行CMOS反相器量測。顯示了環繞式閘極多晶矽無接面式超晶格氧化鉿鋯材料鐵電電晶體在低功耗和高性能應用中的潛力，而超晶格氧化鉿鋯材料的應用有望進一步推進鐵電材料的研究和應用，並在未來的半導體應用中發揮重要的作用。

With the rapid advancements in modern technology, the semiconductor industry has become deeply intertwined with human life. As semiconductor sizes continue to shrink following Moore's Law, various challenges such as physical limitations and difficulties in fabrication processes have arisen, becoming crucial issues to overcome. Throughout history, researchers have proposed methods to mitigate short-channel effects, including altering gate structures, using high-k dielectric materials for the oxide layer, and employing junctionless transistors, among others.
This thesis focuses on using superlattice hafnium zirconium oxide (SL HZO) and hafnium zirconium oxide (HZO) materials in Metal-Ferroelectric-Metal (MFM) capacitors and Ferroelectric Poly-Si Junctionless Nanosheet Gate-all-around Field-effect-transistor (JL Poly-Si Fe-GAAFETs), respectively. Material analyses confirmed the ferroelectric properties of both materials, with SL HZO showing superior characteristics. Capacitance measurements revealed higher dielectric constant and remanent polarization in SL HZO, resulting in superior MFM capacitor performance.
In the study of transistors, SL HZO as the gate oxide of Ferroelectric Poly-Si Junctionless Nanosheet Gate-all-around Field-effect-transistors demonstrated better performance, with smaller subthreshold swing, higher ION/IOFF ratio, lower drain-induced barrier lowering (DIBL), and higher carrier mobility. Successful fabrication of p-type transistors using SL HZO as the gate oxide and demonstration of CMOS inverters further emphasized the potential of SL HZO for low-power and high-performance applications, contributing to the advancement of ferroelectric materials research and their applications in future semiconductor devices.
In conclusion, this thesis explores the challenges posed by semiconductor scaling and presents the potential benefits of utilizing SL HZO materials in enhancing device performance. The findings contribute to the progress of current semiconductor technology and inspire further research in this field.

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