一個1.2V 5.1GHz內建自我測試三種狀態快速鎖定同時消除小數指狀突波式鎖相迴路

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研究生：	邱仕文 Chiu, Shih-Wen
論文名稱：	一個1.2V 5.1GHz內建自我測試三種狀態快速鎖定同時消除小數指狀突波式鎖相迴路 A 1.2V 5.1GHz BIST Triple-State Very Fast Locking with Fractional-Spur-Eliminated PLL
指導教授：	張慶元 Chang, Tsin-Yuan
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2009
畢業學年度：	97
語文別：	英文
論文頁數：	79
中文關鍵詞：	鎖相迴路、快速鎖定、三種狀態、可變頻寬
相關次數：	點閱：2 下載：0
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鎖相迴路 (Phase-Locked Loop, PLL) 廣泛的應用在我們所設計的IC產品上。在現今的無線通訊系統中，特別在於相位雜訊方面的要求格外嚴謹，然而影響相位雜訊好壞，除鎖相迴路中輸出級的電壓控制震盪器 (Voltage-Control Oscillator) 的限制外，在系統中，通常是藉由調整調整低通濾波器 (Low-Pass Filter) 的電組和電容值，以降低迴路頻寬的方式，得到較佳的相位雜訊免疫能力，然而在降低迴路頻寬之下，付出的是過長的鎖定時間 (Locking Time) ，延長鎖相迴路達到穩態的時間，在做大頻率跳躍的系統中，需要較長的再鎖定時間。
現今使用鎖相迴路中，藉由非整數除頻器所組成的非整數型鎖相迴路 (Fractional-N PLL) 和傳統整數型鎖相迴 (Integer-N PLL) 路相比，能得到更多頻率輸出頻段，所應用的範圍更加廣泛，但是非整型鎖相迴路是以類似頻率補償的方式，在巨觀的時間上得到所需要的輸出頻率，但是微觀上頻率卻是週期性的變化，所以在輸出頻率上會產生非理想的小數指狀突波 (fractional spurs) ，一般抑制的方法是藉由增加突波抑制電路來降低小數指狀突波對相位雜訊的影響，這同樣意味著需要增加電路設計的複雜度。
隨著製程技術的不斷演進，伴隨著操作頻率的提高和對於降低功率消耗的要求，降低操作電壓是不可避免的議題，但在低電壓的操作下，需要在電路操作速度 (operating speed) 和起始電壓 (Threshold Voltage, Vth) 上做更審慎的思量，甚至在更先進製程中，所產生的漏電流問題對於電路的影響也越發巨大。
本研究主要是藉由非整數型鎖相迴路和整數型鎖相迴路間的轉換，達到以大寬頻非整數鎖相迴路達到快速鎖定，切換成中頻寬整數型鎖相迴路以消除非理想性的小數指狀突波，最後以小頻寬的整數型鎖相迴路達到鎖定，將除頻數 (N) 導入可調整參數中，可增加可條頻寬的範圍以達到降低鎖定時間目的，同時也可藉由非整數鎖相迴路轉換為整數型鎖相迴路，同時達到消除小數指狀突波，最後的小頻寬整數模式可得到預設最低相位雜訊的目的。
所提出的1.2伏相位抖動抖動量測器 (Jitter Measurement, JM)，可依據相位誤差大小控制對於電容放電至目標電壓所需要的時間，判斷以上所提出三種狀態的切換點，相位抖動抖動量測器為一種平均時間轉換電壓 (Time-to-Voltage) 的系統，擁有比一般鎖相迴路中使用延遲單元 (Delay cell) 所組成的相位誤差偵測器擁有更佳擴充性和應用性以及抗製變異能力，再藉由所提出的簡易頻寬控制單元 (Band Width Control Unit, BWCU) 即可達到控制訊號的產生。

中文摘要………………………………………………………………I
Abstract………………………………………………………………III
List of Contents……………………………………………………V
List of Figures…………………………………………………… VIII
List of Tables………………………………………………………XII
Chapter 1.  Introduction…………………………………………  1
       1.1 Motivation……………………………………………   1
       1.2 Technique review of bandwidth control PLL……  4
       1.3 Thesis design target………………………………   9
Chapter 2.Phase Locked Loop and Dynamic Bandwidth Control 10
       2.1 PLL basic structure…………………………………  10
       2.2 PLL ideal linear model analysis…………………  11
       2.3 Noise analysis………………………………………… 13
         2.3.1 Phase noise analysis…………………………… 14
         2.3.2 Jitter……………………………………………… 16
       2.4 Loop bandwidth and locking time ………………… 18
        2.5 Dynamic (adaptive) bandwidth PLL………………  20
        2.6 Fractional-N and Integer-N transfer…………… 23
        2.7 Bandwidth control with frequency divider number
            N………………………………………………………… 25
Chapter 3.Proposed Adaptive PLL………………………………… 28
       3.1 Proposed triple bandwidth control PLL…………  29
         3.1.1 Proposed Triple bandwidth control flow…… 31
       3.2 Proposed Fractional-N PLL parts…………………  35
         3.2.1 PFD (Phase-Frequency-Detector)……………… 36
         3.2.2 CP (Charge Pump)………………………………… 38
         3.2.3 LF (Low-pass Filter)…………………………… 41
         3.2.4 VCO (Voltage Control Oscillator)…………… 42
         3.2.5 Divider for VCO…………………………………  46
         3.2.6 Fractional divider and integer divider…… 47
       3.3 Jitter Measurement…………………………………… 53
         3.3.1 Jitter Measurement operation flow…………  54
         3.3.2 Integrated with proposed triple-state PLL  57
         3.3.3 Low supply voltage operation………………… 59
       3.4 Proposed Bandwidth control unit (BWCU)………… 64
Chapter 4.Simulation Result and Comparison…………………  66
       4.1 Simulation result……………………………………  67
       4.2 Specification…………………………………………  71
       4.3 Layout view……………………………………………  72
       4.4 Comparison……………………………………………… 73
Chapter 4.  Conclusion……………………………………………  75
Bibliography…………………………………………………………  76

                                

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