近年來，電子產品不僅要追求高速、高效能，必須兼備低耗電與低成本。現今全球各大半導體廠面對元件持續的微縮，除了製程上可行性限制外，開發出一個滿足高性能與可擴展性的目標相當重要。依據目前半導體產業的製程技術，
2015ITRS2.0提出符合未來趨勢的新應用，主要焦點為使用Ge與III-V材料取代傳統的矽，主要原因為Ge與III-V材料具有較高的遷移率。並提出結合3D堆疊元件與低功耗元件將會是微縮的第三世代趨勢"3D Power Scaling"。而且因為面對閘極長度的持續微縮，為了克服所面臨的短通道效應及持續提升電晶體性能，在7奈米節點以下，有些公司已經主張不再打通道的離子佈植，而傳統反轉式電晶體的汲極和源極因為熱製程可能擴散至通道造成漏電，因此在2015ITRS2.0的預測下未來可能改採無接面式電晶體來抑制短通道效應。

在此篇論文研究中，主要探討的是在5奈米節點下的電晶體趨勢發展分析，包含了預測有可能會實現在未來的電晶體技術，因此本篇論文會分為三個部份去探討，第一部分為使用矽鍺通道的鰭式電晶體研究，在傳統鰭式電晶體的通道摻雜鍺來提升其載子遷移率，並且也會對漏電造成影響，且由於鍺的半導體特性較偏向於P，因此在應用在PMOS較多，故在這部分會針對NMOS去做探討。第二部分為在傳統鰭式電晶體結構下的井摻雜優化，透過退後井製程的摻雜，不僅可以降低漏電流，更有效抑制因製程變異所產生的電性變動。因此在這部分要研究的是對於調變退後井製程的摻雜能量和劑量，找出此製程對漏電抑制的原因以及最佳化。第三部分為研究對於未來的堆疊趨勢的研究，在未來，無論是電晶體層級的堆疊或是電路層級，堆疊已然成為最有可能實現的手段，其優點包含全包覆式閘極對於通道控制更有利，以及向上堆疊進一步提升導通電流。因此在這個部分，將會對於堆疊進行模擬，包含電晶體性能、電路速度；在後面還會針對IBM所提出的nanoring結構做進一步分析。

In recent years, the electronic products pursue not only the higher speed and better performance, but also less power consumption and lower cost. The semiconductor ICs manufacturing companies still follow Moore's law to scaling. In addition to processing technology feasibility limits, it is important to develop a target that suffices high performance and scalability. Information processing technology is driving the semiconductor into a broadening spectrum of new applications according to 2015 ITRS 2.0 report. A significant part of the research to further improve device performance is presently concentrated on III-V materials and Ge. These materials promise higher mobility than Si devices. The combination of 3D device architecture and low power device will usher the Era of Scaling, identified in short as “3D Power Scaling”.
In this thesis, the main discussion is the analysis of the trend of transistor development under the sub-5 nm node, including the prediction of the possibility of future realization of transistor technology, so this thesis will be divided into three parts to discuss. The first part is the study of FinFET transistors using SiGe channels. The mole fraction of Ge in the channels will increases the carrier mobility but also leakage. Since the semiconductor characteristics of Ge are more biased toward P, it is more suitable for PMOS applications. Many, so in this part will be discussed for NMOS. The second part is the optimization of well doping under the traditional FinFET structure. Through the doping of the super steep retrograde well process, not only the leakage current can be reduced, but also the electrical variation caused by the process variation can be effectively suppressed. Therefore, in this section, we must study the doping energy and dose for the process of tuning the retrograde well and find out the reasons for this process's suppression of leakage and optimize it. The third part is to study the research on the future stacking trend. In the future, whether stacking at the transistor level or the circuit level, stacking has become the most possible means. The advantages include gate-all-around for channel control. stacking channel upwards further increases the on-current. Therefore, in this section, the stack will be simulated, including transistor performance, circuit speed, and will be further analyzed for the nanoring structure proposed by IBM.

Chapter 1

1-1. ITRS 2.0 roadmap, 2015
1-2. Colinge, J. P. (2012). Junctionless transistors. 2012 IEEE International Meeting for Future of Electron Devices, Kansai.
1-3. J. P. Colinge, C. W. Lee, N. Dehdashti Akhavan, R. Yan, I. Ferain, P. Razavi, A. Kranti and R. Yu, "Junctionless Transistors: Physics and Properties," Semiconductor-On-Insulator Materials for Nanoelectronics Applications (pp.187-200), 2011.
1-4. IEDM, short course 2016.
1-5. S. Takagi, T. Iisawa, T. Tezuka, T. Numata, S. Nakaharai, N. Hirashita, et al., "Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance," IEEE Transactions on Electron Devices, vol. 55, pp. 21-39, 2008.
1-6. Nathan W. Cheung, Handbook Lecture 21, University of California, Berkeley, pp12. Available:https://zh.scribd.com/document/6664335/Lec-21-Basic-Structure-of-CMOS-Inverter
1-7. J. P. Colinge, "Multigate transistors: Pushing Moore's law to the limit," in 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2014, pp. 313-316.
1-8. S. D. Kim, M. Guillorn, I. Lauer, P. Oldiges, T. Hook, and M. H. Na, "Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond," in 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015, pp. 1-3.
1-9. P. Razavi, G. Fagas, I. Ferain, R. Yu, S. Das, and J.-P. Colinge, "Influence of channel material properties on performance of nanowire transistors," Journal of Applied Physics, vol. 111, p. 124509, 2012/06/15 2012.
1-10. C. H. Lee, S. Mochizuki, R. G. Southwick, J. Li, X. Miao, R. Bao, et al., "A comparative study of strain and Ge content in Si1-xGex channel using planar FETs, FinFETs, and strained relaxed buffer layer FinFETs," in 2017 IEEE International Electron Devices Meeting (IEDM), 2017, pp. 37.2.1-37.2.4.
1-11. S. Gupta, V. Moroz, L. Smith, Q. Lu, and K. C. Saraswat, "A group IV solution for 7 nm FinFET CMOS: Stress engineering using Si, Ge and Sn," in 2013 IEEE International Electron Devices Meeting, 2013, pp. 26.3.1-26.3.4.
1-12. P. Feng, S. C. Song, G. Nallapati, J. Zhu, J. Bao, V. Moroz, et al., "Comparative Analysis of Semiconductor Device Architectures for 5-nm Node and Beyond," IEEE Electron Device Letters, vol. 38, pp. 1657-1660, 2017.

Chapter 2

2-1. User's Manual for Synopsys Sentaurus Device, 2015
2-2. C. H. Lee, S. Mochizuki, R. G. Southwick, J. Li, X. Miao, R. Bao, et al., "A comparative study of strain and Ge content in Si1-xGex channel using planar FETs, FinFETs, and strained relaxed buffer layer FinFETs," in 2017 IEEE International Electron Devices Meeting (IEDM), 2017, pp. 37.2.1-37.2.4.
2-3. T. Tezuka, S. Nakaharai, Y. Moriyama, N. Hirashita, N. Sugiyama, A. Tanabe, et al., "Hole-Mobility Enhancement in Ge-Rich Strained SiGe-on-Insulator pMOSFETs at High Temperatures," IEEE Transactions on Electron Devices, vol. 54, pp. 1249-1252, 2007.
2-4. O. Weber, T. Irisawa, T. Numata, M. Harada, N. Taoka, Y. Yamashita, et al., "Examination of Additive Mobility Enhancements for Uniaxial Stress Combined with Biaxially Strained Si, Biaxially Strained SiGe and Ge Channel MOSFETs," in 2007 IEEE International Electron Devices Meeting, 2007, pp. 719-722.
2-5. T. Tezuka, E. Toyoda, S. Nakaharai, T. Irisawa, N. Hirashita, Y. Moriyama, et al., "Observation of Mobility Enhancement in Strained Si and SiGe Tri-Gate MOSFETs with Multi-Nanowire Channels Trimmed by Hydrogen Thermal Etching," in 2007 IEEE International Electron Devices Meeting, 2007, pp. 887-890.
2-6. J. Oh, I. Ok, C. Y. Kang, M. Jamil, S. H. Lee, W. Y. Loh, et al., "Mechanisms for low on-state current of Ge (SiGe) nMOSFETs: A comparative study on gate stack, resistance, and orientation-dependent effective masses," in 2009 Symposium on VLSI Technology, 2009, pp. 238-239.
2-7. H. Takeda, M. Kawada, K. Takeuchi, and M. Hane, "Analyses and optimization of strained-SiGe on Si pMOSFETs by using full-band device simulation," in 2009 Symposium on VLSI Technology, 2009, pp. 20-21.
2-8. M. H. Lee, S. T. Chang, S. Maikap, C. Y. Peng, and C. H. Lee, "High Ge Content of SiGe Channel pMOSFETs on Si (110) Surfaces," IEEE Electron Device Letters, vol. 31, pp. 141-143, 2010.

Chapter 3

3-1. User's Manual for Synopsys Sentaurus Device, 2015
3-2. S. Gupta, V. Moroz, L. Smith, Q. Lu, and K. C. Saraswat, "A group IV solution for 7 nm FinFET CMOS: Stress engineering using Si, Ge and Sn," in 2013 IEEE International Electron Devices Meeting, 2013, pp. 26.3.1-26.3.4.
3-3. R. Xie, P. Montanini, K. Akarvardar, N. Tripathi, B. Haran, S. Johnson, et al., "A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels," in 2016 IEEE International Electron Devices Meeting (IEDM), 2016, pp. 2.7.1-2.7.4.
3-4. N. Xu, H. Takeuchi, N. Damrongplasit, R. J. Stephenson, X. Huang, N. W. Cody, et al., "Extension of Planar Bulk n-Channel MOSFET Scaling With Oxygen Insertion Technology," IEEE Transactions on Electron Devices, vol. 61, pp. 3345-3349, 2014.
3-5. Y. C. Chou, C. C. Hsu, C. T. Chun, C. H. Chou, M. L. Tsai, Y. H. Tsai, et al., "Integration of hetero-structure body-tied Ge FinFET using retrograde-well implantation," in 2016 IEEE 16th International Conference on Nanotechnology (IEEE-NANO), 2016, pp. 142-144.

Chapter 4

4-1. User's Manual for Synopsys Sentaurus Device, 2015
4-2. P. Feng, S. C. Song, G. Nallapati, J. Zhu, J. Bao, V. Moroz, et al., "Comparative Analysis of Semiconductor Device Architectures for 5-nm Node and Beyond," IEEE Electron Device Letters, vol. 38, pp. 1657-1660, 2017.
4-3. B.-H. Lee, M.-H. Kang, D.-C. Ahn, J.-Y. Park, T. Bang, S.-B. Jeon, et al., "Vertically Integrated Multiple Nanowire Field Effect Transistor," Nano Letters, vol. 15, pp. 8056-8061, 2015/12/09 2015.
4-4. S. D. Kim, M. Guillorn, I. Lauer, P. Oldiges, T. Hook, and M. H. Na, "Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond," in 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015, pp. 1-3.
4-5. J.-P. Colinge, C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, et al., "Nanowire transistors without junctions," Nature Nanotechnology, vol. 5, p. 225, 02/21/online 2010.
4-6. H. B. Chen, Y. C. Wu, C. Y. Chang, M. H. Han, N. H. Lu, and Y. C. Cheng, "Performance of GAA poly-Si nanosheet (2nm) channel of junctionless transistors with ideal subthreshold slope," in 2013 Symposium on VLSI Technology, 2013, pp. T232-T233.
4-7. S. Migita, Y. Morita, M. Masahara, and H. Ota, "Electrical performances of junctionless-FETs at the scaling limit (LCH = 3 nm)," in 2012 International Electron Devices Meeting, 2012, pp. 8.6.1-8.6.4.
4-8. V. Thirunavukkarasu, Y. R. Jhan, Y. B. Liu, and Y. C. Wu, "Characteristics of inversion, accumulation and junctionless mode silicon N-type and P-type bulk FinFETs with optimized 3-nm nano-fin structure," in 2015 Silicon Nanoelectronics Workshop (SNW), 2015, pp. 1-2.
4-9. S. Guin, M. Sil, and A. Mallik, "Comparison of Logic Performance of CMOS Circuits Implemented With Junctionless and Inversion-Mode FinFETs," IEEE Transactions on Electron Devices, vol. 64, pp. 953-959, 2017.
4-10. T. Huynh-Bao, S. Sakhare, J. Ryckaert, A. Spessot, D. Verkest, A. Mocuta, "SRAM Designs for 5nm Node and Beyond: Opportunities and Challenges," IEEE Transactions on Electron Devices, 2017.
4-11. D. Jie and H. S. P. Wong, "Metrics for performance benchmarking of nanoscale Si and carbon nanotube FETs including device nonidealities," IEEE Transactions on Electron Devices, vol. 53, pp. 1317-1322, 2006.
4-12. Robert Puers, Livio Baldi, Marcel Van de Voorde, Sebastiaan E. van Nooten, Nanoelectronics: Materials, Devices, Applications, 2 Volumes, edited by W. Robert Puers, Livio Baldi, Marcel Van de Voorde, Sebastiaan E. van Nooten, Wiley-VCH, Germany, 2017.