網狀連接處理器陣列之記憶體內建同儕修復架構

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研究生：	董志宣 Tung, Chih-Hsuan
論文名稱：	網狀連接處理器陣列之記憶體內建同儕修復架構 A Memory Built-In Peer-Repair Architecture for Mesh-Connected Processor Array
指導教授：	吳誠文 Wu, Cheng-Wen
口試委員:	黃錫瑜 Huang, Shi-Yu 呂學坤 Lu, Shyue-Kung 李昆忠 Lee, Kuen-Jong
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2021
畢業學年度：	109
語文別：	英文
論文頁數：	41
中文關鍵詞：	內嵌式記憶體、記憶體內建自我修復、記憶體內建同儕修復、網狀連接處理器陣列、記憶體修復、記憶體測試、備援分析、系統晶片、備援配置、動態隨機存取記憶體、良率提升
外文關鍵詞：	embedded memory, memory built-in self-repair (MBISR), memory built-in peer-repair (MBIPR), mesh-connected processor array, memory repair, memory testing, redundancy analysis, SoC, spare allocation, SRAM, yield improvement
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近年來，在人工智慧應用的推動下，網狀連接處理器陣列已成為流行的高效能人工智慧運算架構，例如IBM TrueNorth、Intel Loihi、Cerebras WSE、Google TPU等。該架構除了處理器核心以外，系統中的記憶體在性能和功耗方面也有著至關重要的地位，因嵌入式記憶體通常佔據這些晶片總面積的2/3以上，從而主導運算晶片的良率和可靠度。記憶體內建自我修復（MBISR）已被認為是測試和修復處理器核心中嵌入式記憶體的可行解決方案。但是，MBISR沒有發揮網狀連接處理器陣列的連接特性優勢。在本文中，我們提出了一種記憶體內建同儕修復（MBIPR）架構，該架構使處理器核心能夠與網狀連接陣列中的相鄰核心共享其備用記憶體。實驗結果顯示，提出的MBIPR的修復率優於原始MBISR。並且與MBISR相比，MBIPR將備用記憶體的利用率提高了2.1到8.1倍、系統壽命提高了2.1到7.9倍，而面積成本僅增加了0.2-0.9％。

Driven by artificial intelligence (AI) applications in recent years, the mesh-connected processor array has become a popular high-performance AI computing architecture, such as IBM TrueNorth, Intel Loihi, Cerebras WSE, Google TPU, etc. In addition to processor cores, however, it is well known that memories in the system play a critical role in performance and power consumption, so normally the embedded memories occupy more than 2/3 of the overall area of these chips, which in turn dominate the yield and reliability of the computing chips. Memory built-in self-repair (MBISR) has been considered a feasible solution for test and repair of embedded memories in the respective processor cores. However, so far MBISR does not take advantage of the regular topology of the mesh-connected processor array. In this paper, we propose a memory built-in peer-repair (MBIPR) architecture that enables the processor core to share its spare memories with the neighboring cores in the mesh-connected array. Experimental results show that the repair rate of the proposed MBIPR outperforms that of the original MBISR. Compared with MBISR, MBIPR increases the spare utilization by 2.1 to 8.1 times, and the lifetime by 2.1 to 7.9 times, with only about 0.2-0.9% higher area overhead.

摘要    i
Abstract    ii
Contents    iii
List of Figures    v
List of Tables    vii
Chapter 1  Introduction    1
1.1    Motivation    1
1.2    Introduction to Mesh-Connected Processor Arrays    3
1.4    Organization    4
Chapter 2  Background    5
2.1    Redundant-Core Repair for Mesh-Connected Processor Arrays    5
2.2    Memory Built-In Self-Test (MBIST)    6
2.2.1    Controller Architecture    9
2.2.2    Sequencer Architecture    9
2.2.3    Test Pattern Generator (TPG) Architecture    10
2.2.4    BIST Intermediate Description (BID) Format    11
2.2.5    BIST Circuit Compilation Flow    13
2.3    Memory Built-In Self-Repair (MBISR)    13
2.3.1    The Essential Spare Pivoting (ESP) Algorithm    14
2.3.2    BRAINS+: The MBIST/R Generator    17
Chapter 3  Proposed Method    19
3.1    MBIPR for Mesh-Connected Processor Arrays     19
3.2    MBIPR Architecture    20
3.3    MBIPR in the Test Mode and the Normal Mode    21

Chapter 4  Experimental Results    25
4.1    Evaluation of Repair Rate    25
4.2    Evaluation of Lifetime and Spare Utilization    27
4.3    Area Overhead    32
4.4    Timing and Power Overhead    34
4.5    I/O Overhead    35
Chapter 5  Conclusion and Future Work    37
5.1    Conclusion    37
5.2    Future Work    37
Bibliography    38


                                

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