具功率意識AES加密器之設計｜國立清華大學博碩士論文庫

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研究生：	沈政昊 Zheng-Hao Shen
論文名稱：	具功率意識AES加密器之設計 Design of a Power-Aware AES Cipher
指導教授：	黃稚存 Chih-Tsun Huang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2007
畢業學年度：	95
語文別：	中文
論文頁數：	67
中文關鍵詞：	先進加密標準、網路安全、密碼學超大型積體電路設計、功率意識
外文關鍵詞：	AES, Network Security, Cryptographic VLSI Design, Power-Aware
相關次數：	點閱：2 下載：0
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由於現今無線傳輸、多媒體等網路應用的需求迅速成長，強健的安全機制是越來越重要了，因此資料安全在通訊系統上相對扮演著重要的角色，而對於不同的應用，為了達到多樣化的高產能、低成本、以及彈性化的安全運算設計，能源的使用效率是最重要的設計關鍵，尤其是對於可攜式裝置上的應用。具功率意識的設計方法可達到效能需求，並且能有效的減少功率消耗，而具功率意識的設計系統不只能夠提供低功耗的特性，同時也能依據不同條件下的需求，有效的去控制整體的電源消耗。在這篇論文中，我們提出了一個具功率意識的AES加密器之設計，此設計的架構中包含了AES加密器、電源管理控制器以及非同步傳輸介面等。同時我們依據先前成功量測的AES加解密晶片特性，去分析以及探討非同步傳輸介面的效能以及限制等，而實驗結果顯示出具功率意識的AES加密器之設計不但能降低功耗並且也兼顧了效能，在未來能夠廣泛應用在各種的安全設計上。

The rapid increasing demand of widespread wireless, multimedia, and data networking applications has led an urgent need of the robust secure mechanism. Data security therefore plays a more and more important role for the critical communication system. Because of the heterogeneity of the applications, a large variety of the security ciphers with high throughput, small area and cost, and flexibility and scalability is required. For the portable devices, additionally, energy efficiency is the most crucial. Therefore the power-aware design methodology is expected to minimize the power consumption with the fulfillment of the performance requirement. A power-aware system is not only a conventional low-power design, but also a design that can adaptively adjust its power consumption to meet specific conditions, such as different throughput requirements, operation modes, user preferences, and operating environments. In this thesis, we present a power-aware AES cipher design. In addition to the design and implement of a high-throughput full featured AES cipher core, a power-aware architecture is proposed. The power-aware architecture consists of a power management controller to monitor and control the different power modes of the AES core, and an interface wrapper to manipulate the data transaction between multiple power/frequency domains dynamically. With the measured characteristics from our AES test chip, we analyze and discuss the performance and limitation using the proposed asynchronous interface wrapper. The experimental results show that our AES cipher proves a high performance with rich features, and the proposed power-aware architecture and methodology can further extend its energy efficiency for a wide range of security applications.

Contents
Introduction
1 Power-Aware AES Cipher
2 Proposed Approach
3 Thesis Organization
Related Works
1 Previous Works
1.1 AES Design
1.2 AES Chip
1.3 SystemC Implementation
2 AES Encryption and Decryption Procedure
2.1 SubBytes() Transformation
2.2 ShiftRows() Transformation
2.3 MixColumns() Transformation
2.4 AddRoundKey() Transformation
2.5 Key Expansion
2.6 Different AES Operation Mode
2.7 ECB Mode
2.8 CBC Mode
2.9 CTR Mode
2.10 CCM Mode
3 Bus Protocol Specification
3.1 Bus Interconnection
3.2 AMBA AHB Operation
3.3 Basic transfer
4 Power-Aware Design
4.1 Dynamic Power Management
4.2 Low-Power Design
4.3 Power-Aware Buffer Cache
5 Power Management
5.1 Dynamic Power Management System Platform Design
Proposed Power-Aware AES Cipher
1 AES Design
1.1 AES Throughput Estimation
2 Traditional Design of the Asynchronous FIFO
2.1 Metastability of Multi-clock Domains
2.2 Asynchronous Synchronization Summary
2.3 Synchronizer Design of Asynchronous FIFO
3 Power-Aware Design
3.1 Multi-Clock Wrapper Design
3.2 The Architecture of Power-Aware AES Wrapper Design
3.3 Asynchronous FIFO Design of AHB Wrapper
3.4 Asynchronous FIFO Design of AES Wrapper
Implementation, Experiment and Analysis
1 AES Design
1.1 AES Analysis and Discussion
2 AES Chip
2.1 Testing Flows
2.2 Testing Result
2.3 Power Analysis
2.4 Chip Specifications
3 Power-Aware AES Design
3.1 The Performance of Power-Aware AES
3.2 Performance Analysis of Power-Aware AES
Conclusions and Future Works
1 Conclusions
2 Future Works

                                

[1] Clifford E. Cummings and Peter Alfke, “Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons”, 2002, pp. 1–18, SNUG San Jose.
[2] National Institute of Standards and Technology (NIST), Data Encryption Standard (DES), FIPS, Oct. 1999.
[3] National Institute of Standards and Technology (NIST), Advanced Encryption Standard (AES), National Technical Information Service, Springfield, VA 22161, Nov. 2001.
[4] R. L. Rivest, A. Shamir, and L. Adleman, “A method for obtaining digital signatures and public-key cryptosystems”, Communications of the ACM, vol. 21, no. 2, pp. 120– 126, Feb. 1978.
[5] USA Microprocessor Standards Committee of the IEEE Computer Society, IEEE 1363 Standard Specifications for Public-Key Cryptography, IEEE Computer Society, Aug. 2000.
[6] ARM Corporation, AMBA Specification(Rev 2.0), May 1999.
[7] I. Verbauwhede, P. Schaumont, and H. Kuo, “Design and performance testing of a 2.29 Gb/s Rijndael Processor”, IEEE Jour. of Solid-State Circuits, pp. 569–572, 2003.
[8] A. Hodjat, D. Hwang, B. Lai, K. Tiri, and I. Verbauwhede, “A 3.84 Gbits/s AES Crypto Coprocessor with Modes of Operation in a 0.18-μm CMOS Technology”, in Proc. Great Lakes Sym. on VLSI (GLSVLSI), Apr. 2005.
[9] S. Morioka and A. Satoh, “A 10Gbps full-AES crypto design with a twisted-BDD SBox architecture”, in Proc. IEEE Int’l Conf. on Computer Design (ICCD), Freiburg, Germany, Sept. 2002, pp. 98–103.
[10] A. Hodjat, P. Schaumont, and I. Verbauwhede, “Architectural design feature of a programmable high throughput aes copressor”, in Proc. IEEE Coding and Computing, Oct. 2004.
[11] C.-P. Su, T.-F. Lin, C.-T. Huang, and C.-W. Wu, “A high-throughput low-cost AES processor”, IEEE Communications Magazine, vol. 41, no. 12, pp. 86–91, Dec. 2003.
[12] C.-L. Horng, “An AES cipher chip design using on-the-fly key scheduler”, Master Thesis, Dept. Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan, June 2004.
[13] Design Automation Standards Committee of the IEEE Computer Society, IEEE Std 1666 - 2005 IEEE Standard SystemC Language Reference Manual, 2006.
[14] M. Dworkin, “Recommendation for block cipher modes of operation: The CCM mode for authentication and confidentiality”, Technical report, National Institute of Standards and Technology (NIST), Gaithersburg, MD, May 2004, http://csrc.nist.gov/CryptoToolkit/modes/.
[15] Massoud Pedram and Jan M. Rabaey, Power Aware Design Methodologies, Springer, 2002.
[16] J. Lorch and A. Smith, “Software Strategies for Portable Computer Energy Management”, IEEE Personal Communications, vol. 5, no. 3, pp. 60, June 1998.
[17] Luca Benini and G. De Micheli, Design Techniques and CAD Tools, Springer, Nov. 1997.
[18] Kiat-Seng Yeo, Samir S. Rofail, and Wang-Ling Goh, CMOS/BiCMOS ULSI: Low Voltage, Low Power, Prentice Hall PTR, Dec. 2001.
[19] Euiseong Seo Min Lee, Joonwon Lee, and Jin-Soo Kim, “PABC: Power-Aware Buffer Cache Management for Low Power Consumption”, IEEE Trans. on Computers, vol. 56, no. 4, pp. 488–501, Apr. 2007.
[20] L. Benini, A. Bogliolo, and G. De Micheli, “A Survey of Design Techniques for System-Level Dynamic Power Management”, IEEE Trans. on VLSI Systems, vol. 8, no. 3, pp. 299–316, June 2000.
[21] Wade L. Williams, Philip E. Madrid, and Scott C. Johnson, “Low Latency Clock Domain Transfer for Simultaneously Mesochronous, Plesiochronous and Heterochronous Interfaces”, Mar. 2007, pp. 196–204, Asynchronous Circuits and Systems, 2007. ASYNC 2007. 13th IEEE International.
[22] C.-P. Su, T.-F. Lin, C.-T. Huang, and C.-W. Wu, “A highly efficient AES cipher chip”, in Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), Kitakyushu, Jan. 2003, pp. 561–562, (Design Contest Special Feature Award).
[23] A. Satoh, S. Morioka, K. Takano, and S. Munetoh, “A compact Rijndael hardware architecture with S-box optimization”, in ASIACRYPT 2001. 2001, vol. 2248 of LNCS, pp. 239–254, Springer-Verlag.
[24] Y.-K. Lai, L.-C. Chang, L.-F. Chen, C.-C. Chou, and C.-W. Chiu, “A novel memoryless AES cipher architecture for networking applications”, in Proc. IEEE Circuit and Systems Symp, May 2004.
[25] A. Hodjat and I. Verbauwhede, “Area-throughput trade-offs for fully pipelined 30 to 70 Gbits/s AES processors”, IEEE Trans. on Computers, vol. 55, no. 4, pp. 366–372, Apr. 2006.

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