近年來，非揮發性記憶體的研究發展主要著重在一種以區域儲存電荷為操作機制的電荷擷取型快閃記憶體（Charge-Trap Flash memory）上，此種技術擁有極佳的微縮特性、低電荷漏失，以及高製程相容。由於其區域儲存電荷的特性，電荷不再單純均勻的分布在電荷儲存層中，使得研究其分布情形變得有價值且重要。目前針對電荷擷取型快閃記憶體的側向電荷分布萃取技術已經被提出，此技術最早是從萃取電晶體之介面陷阱以及氧化層電荷改良而來，其萃取步驟通常伴隨著一中和的步驟，本論文的一開始將說明如何在特定的情況下，省略掉這個步驟以提高萃取MOS電晶體中氧化層電荷分布的效率和增加此技術的應用價值。接著我們在分析SONOS快閃記憶體元件側向電荷分布的技術方面，利用源/汲極不對稱的電荷汲引電流搭配一與距離有關的物理模型修正了傳統電荷汲引技術（Charge-Pumping technique）在萃取電荷分布範圍時可能不夠精準的問題，並以此改良後的電荷汲引技術針對各式記憶體常見的寫入（CHEI）抹除（BBHHE）操作機制進行探討，發現提高寫入時的汲極電壓將使得電子注入的總量呈指數增加；而抹除時更高的汲極電壓則是使電洞注入更集中在汲極接面邊緣，一般來說，BBHHE所造成的電洞注入分布的確比CHEI造成的電子分布更靠近汲極邊緣，而此寫抹條件不對稱的現象被研究出是造成此類快閃記憶體耐久度不佳的主因。論文的最後我們將探討此不對稱的寫抹條件在大量寫抹週期後，電荷殘留的情形，進而提出了一新式的抹除脈衝波形來減經這種不對稱的現象，其在抹除週期中新增的兩個緩斜坡最後也證實的確能達到改善元件耐久度的目的。

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