近年來快閃記憶體在非揮發性記憶體的市場上迅速成長，但是傳統浮動閘極快閃記憶體，由於穿隧氧化層在物理上的極限使其發展將面臨極嚴苛的挑戰。因此，電荷陷阱存式快閃記憶體(Charge Trapping Flash) 被研發出，作為替代之新架構元件，且最具未來發展潛力。其記憶體利用深層的介電層能階缺陷來捕捉電荷以進行儲存，又因操作電壓低及與CMOS高度相容的製程，成為現今快閃記憶體元件的發展主流。
本研究在6吋晶圓上整合CMOS製程來研製一新型雙通道電荷陷阱式非揮發性記憶體，元件的製作是透過國家奈米元件實驗室(NDL)無塵室，接著探討元件的操作機制與操作條件，及其在不同元件尺寸寫入/擦拭後的臨界電壓變化，最後探討此新型雙通道電荷陷阱式非揮發性記憶體元件的可行性。

Conventional flash memory has been themainstream VLSI memory for the past decade.However, as the gate length of flash devices scales into nano-scale regime, it is great challenge to continue the original scaling pace of conventional ‘Floating
Gate’ flash memory due to the physical limit of the tunneling oxide and its related reliability issues. To overcome the bottleneck of scalability, the Charge Trapping Flash (CTF) memory offers a promising alternative to further scale flash memory technology.
In this study, a new non-volatile memory cell with dual channels and charge traps is implemented and in CMOS process on 6-inch wafers. The cells were fabricated in the National Nano Device Laboratory(NDL).In this theisi, the memory cell’s operating mechanisms, operating conditions, and threshold voltage shift after program/erase are discussed. Finally, we discuss the feasibility of this new device.

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