A Boolean function can be represented as two-level or multi-level logic. Two-level logic representation in general is not area-efficient while multi-level one is. However, multi-level logic encounters the problem of a longer delay. Nevertheless, bounded multi-level logic, typically three or four levels, has a smaller delay, compared to unbounded one. Projected Sum of Products (P-SOP) is one of bounded multi-level representation. The synthesis of P-SOP representation is based on decomposing the input space with respect to the orthogonal basis xi' xor p(X(i)) and xi xor p(X(i)) where xi is an input variable and p(X(i)) is a function of all variables except xi. Different p(X(i)) may result in different areas after synthesis. Therefore, to obtain a minimal P-SOP circuit, it is important to select an appropriate pair of variable xi and function p(X(i)). In this paper, with applying the Craig's interpolation theorem, we minimize the P-SOP form in one-half input space by considering the second-half input space as don't-care set and vice versa such that the overall circuit is minimized. We also propose a Genetic Algorithm to efficiently determine the pair of xi and p(X(i)). Experimental results show that the proposed approach saves 81% CPU time in searching such a pair as compared to an exhaustive method without sacrificing the optimality.

一個布林函數可以被表示為兩層邏輯電路以及多層邏輯電路。一般說來，兩層邏輯電路表示式在面積最佳化的效率上較不如多層邏輯電路表示式。儘管，傳統三層或四層的有界多層電路比起無界多層邏輯電路有較短的延遲時間。然而，多層邏輯電路仍然必須面臨較長延遲時間的問題。投影積項之和是一種有界多層邏輯表示式。投影積項之和表示式的合成是基於一對正交基底函數來分解布林空間所得。其正交基底函數是由一個輸入變數以及由除了此輸入變數以外的所有輸入變
數所組成的一個投影函數。不同的投影函數會導致合成過後面積的不同。因此，為了得到一個最小的投影積項之和電路，最重要的事情是選擇一組適當的輸入變數與投影函數組合。在此篇論文，我們根據奎內格內插法定理藉由將投影積項之和表示式的一半布林空間當作無差別集合使得另一半的布林空間可以做更多最佳化的處理，反之亦然。所以，整體的電路會透過此方式再次的被縮小化。另外，我們也提出透過基因演算法有效率的決定一對適當的正交基底函數。由實驗數據
可以看出我們提出的方法比起先前的方法在搜尋最佳正交基底函數上平均可以節省81%的CPU時間而不犧牲其最佳解。

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