內嵌式非揮發性記憶體用之低雜訊高輸出電流及電壓電子幫浦

簡易檢索 / 詳目顯示

回結果列表

研究生：	呂婉熒 Lu, Wan-Ying
論文名稱：	內嵌式非揮發性記憶體用之低雜訊高輸出電流及電壓電子幫浦 Low Supply Noise High Output Current Voltage Charge Pump for Embedded Non-Volatile Memory
指導教授：	張孟凡 Chang, Meng-Fan
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 產業研發碩士積體電路設計專班 Industrial Technology R&D Master Program on IC Design
論文出版年：	2010
畢業學年度：	98
語文別：	英文
論文頁數：	82
中文關鍵詞：	電子幫浦、電源雜訊、四種相位時脈控制
外文關鍵詞：	charge pump, power noise, four phase clocking control scheme
相關次數：	點閱：2 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

目前的系統單晶片中，電子幫浦普遍被用在電路內部產生一個比供應電源更高的正電壓或更低的負電壓，應用在非揮發性記憶體的領域中非常廣泛。內嵌式非揮發性記憶體需要高電壓將電子進入懸浮閘極以及高電流完成寫入機制。
隨著CMOS製程技術的進步，電壓供應越來越低，電源穩定度的考量已經變得越來越被重視。在內嵌式非揮發記憶體中，當電子幫浦作週期性時脈交換，產生的電源峰值電流，使其與包裝內部接線處發生電感及電流電阻效應，產生不可小覷之電源雜訊及接地點跳動，在高效能先進記憶體執行寫入驗證造成讀取錯誤及資料保存能力下降，影響良率甚劇。因此，為達到低雜訊的目的，降低消耗功率之首的電子幫浦之電源峰值電流可以有效解決上述問題。在本篇論文中，應用最常被使用的高電流傳遞之四種相位時脈控制機制，我們提出了區域性分佈且新式四種相位時脈控制機制，使每一級的電子幫浦電路分別在不同時間點操作，仍能完成正確相位避免電流倒流，有效地減少峰值電流及包裝線上的電感效應。
低雜訊電子幫浦使用了九十奈米互補式金氧半導體製程技術實現，量測結果顯示其電源雜訊可有效地在操作頻率於一百萬赫茲到一百六十七萬赫茲均降低百分之六十以上，並且比照於傳統四種時脈相位電子幫浦，可提高百分之七的電源功效，僅僅需要多於百分之三的面積。更進一步的話，搭配新式四種時脈相位，此低雜訊電子幫浦將可以達到較高的操作頻率。

Charge pump circuits (CPCs) are commonly used for pumping charge upward to produce higher than the regular supply voltage or downward to negative voltage on a chip, and have been widely used in non-volatile memories (NVMs) for many years since the NVMs require a high voltage to program floating-gate devices.
Power integrity has become more important as scaling down the supply voltage in SOC designs, the largest power noise and ground bounce occur in high voltage generator as CPC for embedded NVMs such as Flash memory, OTP and EEPROM since periodical switching clock s cause serious power peak current and suffer inductive effect on package bond wire. Suppressing power peak current (PPC) is the most key point for a low noise design. This study proposes new 4-phase with distributed local control scheme that each charge pump module operates not at the same time, therefore the peak current would be degraded and switching power noise due to dI/dt is greatly reduced
The Low Noise Charge Pump (LNCP) is fabricated in 90nm CMOS technology. The measurement results demonstrate that the power noise can be reduced more than 60% from 10MHz to 16.7MHz and better power efficiency about 7% comparing to conventional 4-phase CP with less than 3% area penalty. Moreover, LNCP can be achieved to high speed with new 4-phase clock control in the future.

Chapter 1.    Introduction    1
1    Background    1
2    Motivation    1

Chapter 2.    Fundamentals of Charge Pump Circuit    3
1    Previous Charge Pump Circuit    3
1.1    Dickson’s Multiplier    3
1.2    New Charge Pump (NCP)    5
1.3    Pumping Gain Increase (PGI) Circuit    6
2    Limitation and Improvement    7
3    Four Phase Clocking Scheme    8

Chapter 3.    Charge Pump in Non-Volatile Memory    10
1    Non-Volatile Memory Operations    10
1.1    Non-Volatile Memory Characteristic    10
1.2    Bit-by-bit Verify and Program    11
1.3    Specification of High Voltage Block    12
2    Aspects in design CPC for embedded NVM    14
2.1    Area    14
2.2    Operation voltage    14
2.3    Speed    15
2.4    Pumping Ability    16
2.5    Power Efficiency    16
2.6    Power Noise    17
3    Issues of Power Noise and Ground Bounce    18
3.1    Simultaneous Switching Noise (SSN)    18
3.2    Simple Analytic Models    19
3.3    Power Noise Provider of Charge Pump Circuit    19
3.4    Design Challenges of CPC without Larger Power Noise    21

Chapter 4.    Proposed Scheme    24
1    Low Noise Charge Pump Operation    24
1.1    Distributed Local Control    24
1.2    New 4-Phase Clocking Scheme    28
2    Issues of Major Timing Control    30
2.1    Critical Overlapping Timing    30
2.2    Design for New 4-Phase    32
3    Charge Transfer Operation of LNCP    35
4    Characteristic of New 4-Phase    39
4.1    Right Overlapping Timing (ToverR)    39
4.2    Left Overlapping Timing (ToverL)    41
4.3    Optimization    41
5    Performance Improvement    42
5.1    Noise Reduction    42
5.2    Higher Operation Frequency    43

Chapter 5.    Circuit Implementation    44
1    Macro Architecture    44
1.1    Employed 4-phase CP Architecture    44
1.2    Charge Pump cell    46
1.3    Capacitance Calculation    48
2    Local 4-Phase Implementation    48
2.1    New 4-Phase Clock Generator    48
2.2    Local Phases Control Circuit    50
2.3    Delay Element    51
3    Test-Chip Layout Design    52
3.1    LNCP_G1    52
3.2    LNCP_G2    54
3.3    Area Penalty    56

Chapter 6.    Analysis and Comparison    57
1    Performance of Low Noise CP    57
1.1    Power Efficiency    57
1.2    Load Line    59
1.3    Output Voltage    60
1.4    Power Noise Issue    62
2    Comparison with Conventional Work    66
2.1    Operation Frequency    66
2.2    Bench Mark Table of Recent Research    68

Chapter 7.    Experimental results and Conclusions    71
1    Experimental results    71
1.1    Test-chip Photo    71
1.2    Function Testing    72
1.3    Power Noise Reduction    73
1.4    Power Efficiency Improvement    75
2    Conclusions and Future Work    76

References    78

                                

[1] J. F. Dickson, "On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique," IEEE J. Solid-State Circuits, vol. 11, no. 3, pp. 374-378, 1976.
[2] A. Umezawa, et al., "A 5-V-only operation 0.6-μm flash EEPROM with row decoder scheme in triple-well structure," IEEE J. Solid-State Circuits, vol. 27, no. 11, pp. 1540-1546, 1992.
[3] F. Pan and T. Samaddar, "Charge Pump Circuit Design," ed New York: McGraw-Hill, 2006, p. 169.
[4] W. Jieh-Tsorng, et al., "1.2 V CMOS switched-capacitor circuits," in IEEE ISSCC Dig. Tech. Papers, Feb. 1996, pp. 388-389, 479.
[5] W. Jieh-Tsorng and C. Kuen-Long, "Low Supply Voltage CMOS Charge Pumps," in Symp.VLSI Technology Dig. Tech. Papers, 1997, pp. 81-82.
[6] W. Jieh-Tsorng and C. Kuen-Long, "MOS charge pumps for low-voltage operation," IEEE J. Solid-State Circuits, vol. 33, no. 4, pp. 592-597, 1998.
[7] C. Lon-Kou and H. Chih-Huei, "An exponential-folds design of a charge pump styled DC/DC converter," in Proc. IEEE PESC, 2004, pp. 516-520.
[8] C. Lon-Kou and H. Chih-Huei, "High efficiency MOS charge pumps based on exponential-gain structure with pumping gain increase circuits," in IEEE Trans. Power Electronics, 2006, pp. 826-831.
[9] S. Jongshin, et al., "A new charge pump without degradation in threshold voltage due to body effect [memory applications]," IEEE J. Solid-State Circuits, vol. 35, no. 8, pp. 1227-1230, 2000.
[10] L. Hongchin, et al., "A new 4-phase charge pump without body effects for low supply voltages," Proc. IEEE ASICON Dig. Tech.Papers, pp. 53-56. 2002.
[11] Y. Na and M. Hao, "A High Efficiency ALL-PMOS Charge Pump for Low-Voltage Operations," in IEEE ASSCC Dig. Tech. Papers, 2005, pp. 361-364.
[12] J. C. Chen, et al., "A 2.7 V only 8 Mbx16 NOR flash memory," in Symp.VLSI Circuits Dig. Tech. Papers, June 1996, pp. 172-173.
[13] M. Bloch, et al., "High efficiency charge pump circuit for negative high voltage generation at 2 V supply voltage," Proc. Eur. Solid-State Circuits Conf. (ESSCIRC), pp. 100-103. 1998.
[14] Yu Shen Lin, et al., "Four-phase charge pump with lower peak current " U.S. Patent 6573780, Jun 3, 2003.
[15] P. Salsbury, et al., "High performance, MOS EPROMs using a stacked-gate cell," in IEEE ISSCC Dig. Tech. Papers, 1977, pp. 186-187.
[16] R. Kirisawa, et al., "A NAND structured cell with a new programming technology for highly reliable 5 V-only flash EEPROM," in Symp.VLSI Technology Dig. Tech. Papers, 1990, pp. 129-130.
[17] L. Han-Chao, et al., "A 0.26m2 U-Shaped Nitride-Based Programming Cell on Pure 90-nm CMOS Technology," IEDM Dig. Tech. Papers, vol. 28, no. 9, pp. 837-839, 2007.
[18] M. Momodomi, et al., "A 4 Mb NAND EEPROM with tight programmed Vt distribution," IEEE J. Solid-State Circuits, vol. 26, no. 4, pp. 492-496, 1991.
[19] K. Seki, et al., "An 80 ns 1 Mb flash memory with on-chip erase/erase-verify controller," in IEEE ISSCC Dig. Tech. Papers, 1990, pp. 60-61.
[20] D. Wu, et al., "Charge pump system sharing the coupling capacitors for NOR flash memory," in Proc. IEEE ASICON Dig. Tech.Papers, 2003, pp. 466-469 Vol.1.
[21] W. Chi-Chang and W. Jiin-Chuan, "Efficiency improvement in charge pump circuits," IEEE J. Solid-State Circuits, vol. 32, no. 6, pp. 852-860, 1997.
[22] M. Mihara, et al., "A 29mm2 1.8 V-only 16 Mb DINOR flash memory with gate-protected poly-diode (GPPD) charge pump," in IEEE ISSCC Dig. Tech. Papers, 1999, pp. 114-115.
[23] K. Ming-Dou, et al., "Design of negative charge pump circuit with polysilicon diodes in a 0.25 um CMOS process," in Proc. IEEE ASICON Dig. Tech.Papers, 2002, pp. 145-148.
[24] R. Cernea, et al., "A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in 56nm," in IEEE ISSCC Dig. Tech. Papers, 2008, pp. 420-624.
[25] L. Hongchin, et al., "Novel high positive and negative pumping circuits for low supply voltage," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 1999, pp. 238-241 vol.1.
[26] R. Pelliconi, et al., "Power efficient charge pump in deep submicron standard CMOS technology," IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 1068-1071, 2003.
[27] L. Mensi, et al., "A new integrated charge pump architecture using dynamic biasing of pass transistors," in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC), 2005, pp. 85-88.
[28] A. Richelli, et al., "A 1.2-to-8V Charge-Pump with Improved Power Efficiency for Non-Volatille Memories," in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 522-619.
[29] T. Tanzawa, et al., "A Quick Boosting Charge Pump Circuit for High Density and Low Voltage Flash Memories," in Symp.VLSI Technology Dig. Tech. Papers, 1994, pp. 65-66.
[30] P. Favrat, et al., "A high-efficiency CMOS voltage doubler," IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 410-416, 1998.
[31] K. Joung-Yeal, et al., "CMOS Charge Pump With Transfer Blocking Technique for No Reversion Loss and Relaxed Clock Timing Restriction," IEEE Trans. Circuits Syst. II, vol. 56, no. 1, pp. 11-15, 2009.
[32] L. Hoi and P. K. T. Mok, "Switching noise and shoot-through current reduction techniques for switched-capacitor voltage doubler," IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1136-1146, 2005.
[33] L. Hoi and P. K. T. Mok, "An SC Voltage Doubler with Pseudo-Continuous Output Regulation Using a Three-Stage Switchable Opamp," IEEE J. Solid-State Circuits, vol. 42, no. 6, pp. 1216-1229, 2007.
[34] S. Feng, et al., "Regulated Switched-Capacitor Doubler With Interleaving Control for Continuous Output Regulation," IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1112-1120, 2009.
[35] S. S. Sapatnekar and H. Su, "Analysis and optimization of power grids," IEEE Design & Test of Computers, vol. 20, no. 3, pp. 7-15, 2003.
[36] A. V. Mezhiba and E. G. Friedman, "Scaling trends of on-chip power distribution noise," IEEE Trans. Very Large Scale Integr. (VLSI) System, vol. 12, no. 4, pp. 386-394, 2004.
[37] G. Jie, et al., "On-Chip Supply Noise Regulation Using a Low-Power Digital Switched Decoupling Capacitor Circuit," IEEE J. Solid-State Circuits, vol. 44, no. 6, pp. 1765-1775, 2009.
[38] G. Palumbo, et al., "Charge-pump circuits: power-consumption optimization," IEEE Trans. Circuits Syst. I, vol. 49, no. 11, pp. 1535-1542, 2002.
[39] W. Sun-Bo, et al., "Novel low-power DC-DC converter with high-efficiency charge pump circuits," in Proc. IEEE ASICON Dig. Tech.Papers, 2007, pp. 458-460.
[40] L. Hongchin and C. Nai-Hsien, "New four-phase generation circuits for low-voltage charge pumps," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2001, pp. 504-507 vol. 1.
[41] L. Sheng-Yeh and W. Jinn-Shyan, "A high-efficiency CMOS charge pump circuit," Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), vol. 4, no. pp. 406-409 vol. 4, 2001.
[42] C. Lauterbach, et al., "Charge sharing concept and new clocking scheme for power efficiency and electromagnetic emission improvement of boosted charge pumps," IEEE J. Solid-State Circuits, vol. 35, no. 5, pp. 719-723, 2000.
[43] M. Badaroglu, et al., "Digital ground bounce reduction by phase modulation of the clock," in Des. Autom. Conf. (DAC) Dig. Tech. Papers, 2004, pp. 88-93 Vol.1.
[44] C. Meng-Fan and Y. Shu-Meng, "Analysis and Reduction of Supply Noise Fluctuations Induced by Embedded Via-Programming ROM," IEEE Trans. Very Large Scale Integr. (VLSI) System, vol. 17, no. 6, pp. 758-769, 2009.
[45] G. Jie, et al., "On-Chip Supply Noise Regulation Using a Low-Power Digital Switched Decoupling Capacitor Circuit," IEEE J. Solid-State Circuits, vol. 44, no. 6, pp. 1765-1775, 2009.
[46] S. Kim, et al., "Understanding and minimizing ground bounce during mode transition of power gating structures," in IEEE Int. Symp. Low Power Electronics Des. (ISLPED), 25-27 Aug. 2003, pp. 22-25.
[47] M. H. Chowdhury, et al., "Controlling Ground Bounce Noise in Power Gating Scheme for System-on-a-Chip," in IEEE Trans. Very Large Scale Integr. (VLSI) System, 2008, pp. 437-440.
[48] L. Changbo and H. Lei, "Distributed sleep transistor network for power reduction," IEEE Trans. Very Large Scale Integr. (VLSI) System, vol. 12, no. 9, pp. 937-946, 2004.
[49] A. Vittal, et al., "Clock skew optimization for ground bounce control," in IEEE ICCAD Dig. Tech. Papers, 1996, pp. 395-399.
[50] R. Samanta, et al., "Clock Buffer Polarity Assignment for Power Noise Reduction," IEEE Trans. Very Large Scale Integr. (VLSI) System, vol. 17, no. 6, pp. 770-780, 2009.
[51] Y. Kai, et al., "Optimal clock overlapping of four-phase Dickson charge pump for power efficiency improvement," in IEEE ICSICT Dig. Tech. Papers, 2008, pp. 1729-1732.
[52] C. Meng-Fan and S. Shin-Jang, "A Process Variation Tolerant Embedded Split-Gate Flash Memory Using Pre-Stable Current Sensing Scheme," IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 987-994, 2009.
[53] J. Javanifard, et al., "A 45nm Self-Aligned-Contact Process 1Gb NOR Flash with 5MB/s Program Speed," in IEEE ISSCC Dig. Tech. Papers, 2008, pp. 424-624.
[54] K. Wing-Hung, et al., "Charge redistribution loss consideration in optimal charge pump design," Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), pp. 1895-1898 Vol. 2. 2005.
[55] O. Khouri, et al., "Improved charge pump for flash memory applications in triple well CMOS technology," in IEEE Int. Symp. International Symposium Industrial Electronics (ISIE), 2002, pp. 1322-1326 vol.4.
[56] G. Palumbo and D. Pappalardo, "Charge Pump Circuits: An Overview on Design Strategies and Topologies," IEEE Circuits and Systems Magazine, vol. 10, no. 1, pp. 31-45, 2010.
[57] J. M. Rabaey, et al., "Digital Integrated Circuits: A Design Perspective," 1st ed NJ: Prentice-Hall Book Company, 1996.
[58] P. Yuk-Wah, et al., "An Asynchronous Cell Library for Self-Timed System Designs," IEICE Transactions on Information and Systems, vol. E80-D, no. 3, pp. 296-305, Mar. 1997.
[59] K. Gyudong, et al., "A low-voltage, low-power CMOS delay element," IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 966-971, 1996.
[60] T. Yamazoe, et al., "A charge pump that generates positive and negative high voltages with low power-supply voltage and low power consumption for non-volatile memories," Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), pp. 988-991. 2009.

全文公開日期本全文未授權公開 (校內網路)
全文公開日期本全文未授權公開 (校外網路)

簡易檢索 / 詳目顯示

相關論文