高介電係數介電質材料應用於互補式電晶體、金氧金電容與金屬-氧化層-氮化層-氧化層-矽結構非揮發態記憶體之研究

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研究生：	林士豪 Lin, Shih-Hao
論文名稱：	高介電係數介電質材料應用於互補式電晶體、金氧金電容與金屬-氧化層-氮化層-氧化層-矽結構非揮發態記憶體之研究 The Investigation of Metal-Gate/High-k CMOSFETs、Metal-Insulator-Metal Capacitor and MONOS Non-Volatile Memory Applying High-k Dielectric Materials
指導教授：	葉鳳生 Yeh, Fon-Shan 荊鳳德 Chin, Albert
口試委員:
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering
論文出版年：	2009
畢業學年度：	97
語文別：	英文
論文頁數：	124
中文關鍵詞：	高介電係數介電質材料、互補式電晶體、金氧金電容結構、非揮發態記憶體
外文關鍵詞：	High-k dielectric materials, CMOSFETs, MIM Capacitor, Non-Volatile Memory
相關次數：	點閱：3 下載：0
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根據國際半導體技術藍圖制定會(ITRS)，為了有效降低晶片的面積與節省成本，邏輯與記憶體元件尺寸必須不斷的微縮。而傳統介電層材料二氧化矽(SiO2)應用於相關奈米元件的主要挑戰，在於縮減電子元件尺寸下，將可能帶來極高的漏電流，導致元件特性失效。對於新興的單晶片系統(SoC)積體電路設計來說，持續降低CMOS元件中的閘極絕緣層與非揮發態記憶體中的穿遂氧化層，以提高元件密度及降低操作電壓，更是一項嚴峻的挑戰。在此情況下，高介電係數介電質材料的開發似乎是唯一的選擇，近年來，高介電係數介電質材料應用在邏輯與記憶體元件上，已成為半導體產業最重要的研究之ㄧ。在本論文中，吾人將探討數種高介電係數介電質材料在互補式金氧半電晶體(CMOSFETs)、金氧金電容(MIM Capacitor)與金屬-氧化層-氮化層-氧化層-矽(MONOS)非揮發態記憶體(Non-Volatile Memory)等元件上的研究與應用。

首先，我們將高介電係數介電質材料應用在邏輯元件MOSFETs上，研發出氮化鉭(TaN)/氧化鈦鑭(LaTiO) n型金氧半電晶體，與氮化鉭(TaN)/銥(Ir)/氧化鈦鑭(LaTiO) p型金氧半電晶體，分別在0.63與0.66奈米的等效氧化厚度(EOT)下，具有0.12與 -0.17伏特的低臨界電壓，且在電場0.8V/cm下，分別具有126 與 54 cm2/Vs之載子移動率。上述元件是利用簡單自我對準及閘極優先之積體電路製程，並且應用源極及汲極自動對準之固態擴散製程(Solid-Phase Diffusion，SPD)方法，此方法是為了利用較低的製程溫度來控制高介電係數介電質的介面反應。

其次，對於金氧金電容(MIM Capacitors)的應用，我們提出利用高介電係數介電質材料氧化鈦(TiO2)堆疊氧化鋯(ZrO2)，並使用高功函數鎳(Ni)當作上電極的金氧金電容(MIM Capacitors)結構。此種堆疊結構比只有氧化鋯(ZrO2)的金氧金電容(MIM Capacitors)結構，在125oC的環境下具有較低的8x10-8 A/cm2的漏電且仍保有38 fF/um2的高電容密度。此良好的元件特性是由於在厚度9.5奈米的氧化鈦(TiO2)/氧化鋯(ZrO2)上有較低的電場而使漏電降低，而氧化鈦(TiO2)比氧化鋯(ZrO2)具有較高的高介電係數58，使得此推疊結構仍保有高的電容密度。另外，我們也探討此元件在定電壓下的電場應力測試的可靠度。而我們發現隨著增加推疊在氧化鋯(ZrO2)上的氧化鈦(TiO2)厚度，可以改善在125oC的環境下漏電流、電容的變動程度與可靠度。

最後，我們也將高介電係數介電質材料應用於非揮發態記憶體元件。我們研發出一種新型「陷井式技術」非揮發態快閃記憶體(CTEF)，在厚度只有5奈米的氮化矽(Si3N4)之捕陷層，仍然具有相當大的記憶視窗及良好的電荷存儲能力特性。此元件在快速100毫秒和電壓16伏特的條件操作下，可得到5.6伏特的記憶視窗，在150oC的環境下，其十年的資料儲存能力，仍然可以維持在3.8伏特。上述記憶體元件特性是來自利用淺-深補陷能階的氮化矽(Si3N4)-氮氧化鉿(HfON)之捕陷層結構設計。

According to International Technology Roadmap for Semiconductor (ITRS), logic and memory devices are being continuously scaled down to reduce the area of the chip and the cost. However, traditional dielectric material SiO2 will face the physical limitation of nano device – large leakage current and device will fail. This scaling issue is a formidable challenge especially for emerging system-on-chip (SoC) integrated circuit designs in which a continuously scaling of gate dielectrics for complementary metal oxide semiconductor and tunneling oxide for non-volatile memory is needed to have high density and low operating voltage. To meet this requirement, high dielectric constant (k) materials provide the only solution since decreasing the dielectric thickness (t) degrades both the leakage current and devices performance. In recent years, logic and memory devices applying high dielectric constant (k) materials become one of the most important researches in the semiconductor industry. In this dissertation, we will investigate the application of several high-k dielectric materials for metal-gate/high-k CMOSFETs、MIM Analog-RF/DRAM Capacitors and MONOS non-volatile memory (NVM).

First of all, we demonstrate low Vt of 0.12 and -0.17 V, in dual [TaN-TaN/Ir]/LaTiO n- and p-MOS at 0.63 and 0.66 nm EOT, with good 0.8 MV/cm mobility of 126 and 54 cm2/Vs. This was achieved using Ni-induced solid-phase diffusion to lower high-k interface reaction, with simple self-aligned and gate-first process, compatible with current VLSI.

Next, for metal-insulator-metal (MIM) capacitors using high-k dielectric materials for Analog-RF/DRAM, we have fabricated high-k Ni/TiO2/ZrO2/TiN metal-insulator-metal (MIM) capacitors. A low leakage current of 8x10-8 A/cm2 at 125oC was obtained with a high 38 fF/um2 capacitance density and better than ZrO2 MIM capacitors. The excellent device performance is due to the lower electric field in 9.5 nm thick TiO2/ZrO2 devices to decrease leakage current and the higher k of 58 for TiO2 than ZrO2 to preserve the high capacitance density. We also studied the stress reliability of high-k Ni/TiO2/ZrO2/TiN metal-insulator-metal capacitors under constant-voltage stress. The increasing TiO2 thickness on ZrO2 improves the 125oC leakage current, capacitance variation (delta-C/C), and the long term reliability.

Finally, we also applied high-k dielectric materials for non-volatile memory. We report a novel charge-tapping-engineered flash (CTEF) non-volatile memory with very thin 5 nm Si3N4 that has a large 5.6 V initial memory window and 3.8 V 10-year extrapolated retention window at 150oC and under a fast 100 us and +16/-16 V program/erase. These were achieved using shallow- and deep -energy Si3N4-HfON trapping layers that are much better than the memory device characteristics for the similar structure without the extra 0.9 nm EOT HfON layer.

Contents

ABSTRACT (in Chinese)    i
ABSTRACT (in English)    iv
ACKNOWLEDGMENTS    vii
CONTENTS    viii
FIGURE CAPTIONS    xi
TABLE CAPTIONS    xvi

Chapter 1 Introduction    1
1.1 Overview of high-□ gate dielectrics    1
1.2 Overview of metal gate electrodes    3
1.3 Motivation to study logic and memory devices applying
   high-k dielectrics    5
   (A) Logic Metal-Gate/High-k CMOS applications    5
   (B) MIM Analog-RF/DRAM Capacitors applications    6
   (C) MONOS Non-Volatile Memory applications    8
1.4 The measurement of the devices    10
1.5 Innovation and Contribution    12
   (A) Logic Metal-Gate/High-k CMOS    12
   (B) MIM Analog-RF/DRAM Capacitors    13
   (C) MONOS Non-Volatile Memory    13

Chapter 2 Low Threshold Voltage [TaN-TaN/Ir]/LaTiO n-
and p-MOSFETs Incorporating Low-Temperature-Formed
Shallow Junctions    22
2.1 Introduction    22
2.2 Experimental Procedure    23
2.3 Result and Discussion    24
   (A) C-V and J-V characteristics    24
   (B) Low temperature shallow junction formed by SPD    26
   (C) Device characteristics    28
2.4 Conclusion    29

Chapter 3 High k□and High Density Ni/ZrO2/TiN and Ni/TiO2/ZrO2/TiN MIM Capacitors for Analog and Memory Applications    39
3.1 Introduction    39
3.2 Experimental Procedure    41
3.3 Result and Discussion    42
   (A) C-V and J-V characteristics    42
   (B) Material characterization    44
   (C) Current conduction mechanism    44
   (D) delta-C/C, a and reliability    45
3.4 Conclusion    47

Chapter 4 Compare the Performance of Charge-Trapping    Memory with Different Single and Double Quantum Barriers    60
4.1 Introduction    60
4.2 Experimental Procedure    61
4.3 Result and Discussion    63
   (A) Band diagram and P/E characteristics    63
   (B) Retention and endurance    65
4.4 Conclusion    68

Chapter 5 Good Retention and Fast Erase Novel Charge-Trapping-Engineered Non-Volatile Memory with Scaled Si3N4    76
5.1 Introduction    76
5.2 Experimental Procedure    78
5.3 Result and Discussion    78
   (A) Energy band diagram    78
   (B) Program/Erase Characteristics    79
   (C) Retention & Cycling    80
5.4 Conclusion    82

Chapter 6 Conclusion    95

References    98

Vita    120

Publications List    121



Figure Captions

Chapter 1  Introduction
Fig. 1-1.    High-performance logic technology requirements (the international technology roadmap for semiconductors: 2006 update).
Fig. 1-2.    The band offset of popular high-k materials.
Fig. 1-3.    Bond enthalpy for M-O, M-N and M-C in the Periodic Table for thermal stability prediction, with M-O>M-N>M-C in general. The bond enthalpy peaked at La, Hf and Ta.
Fig. 1-4.    Energy band diagram to show the increasing ｜Vt︱ in both n- and p-MOS.
Fig. 1-5.    The work-function of the elements in the Periodic Table. Lanthanides are useful for n-MOS; only Ir and Pt for p-MOS.
Fig. 1-6.    The International Technology Roadmap of analog and mixed-signal capacitors.
Fig. 1-7.    When the tunnel oxide is scaled, the voltage drop across it is reduced for the same programming  voltage. This increases the nitride tunnel barrier, as shown by the light gray area. The benefit from tunnel oxide scaling is significantly reduced due to the nitride barrier.

Chapter 2  Low  Threshold  Voltage [TaN-TaN/Ir]/LaTiO n- and p-MOSFETs Incorporating Low-Temperature-Formed      Shallow Junctions
Fig. 2-1.    (a) C-V and (b) J-V characteristics of TaN/LaTiO/p-Si n-MOS and TaN/Ir/LaTiO/n-Si p-MOS capacitors.
Fig. 2-2.    Cross-sectional TEM of TaN/LaTiO/p-Si n-MOS capacitors (a) after 600 and (b) 900oC RTA.
Fig. 2-3.    Temperature dependence of (a) C-V and J-V characteristics of TaN/LaTiO/p-Si n-MOS capacitors.
Fig. 2-4.    SIMS profile of LaTiO, after various RTA treatments.
Fig. 2-5.    Grazing incidence XRD spectra of LaTiO, after various RTA treatments.
Fig. 2-6.    (a) J-V characteristics of p+/n junction formed by SiO2/Ni/Ga SPD at 550~850oC RTA [2.6]. (b) J-V characteristics of n+/p junction formed by SiO2/Ni/Sb SPD at 600~700oC RTA.
Fig. 2-7.    (a) □Id-Vd and (b) Id-Vg characteristics of self-aligned, gate-first n-and p-MOSFETs, where the LaTiO gate dielectric is treated with a 600oC RTA.
Fig. 2-8.    The electron and hole mobility of the n- and p-MOSFETs extracted from the Id-Vg curves of Fig. 2-7(b).

Chapter 3  High k□and High Density Ni/ZrO2/TiN and Ni/TiO2/ZrO2/TiN MIM Capacitors for Analog and Memory Applications
Fig. 3-1.    Band alignment of high-k dielectrics to Si and Ni electrode. The EC of STO is 0.1 eV below EC of Si .
Fig. 3-2.    (a) C-V and (b) J-V characteristics of various Ni/STO/TaN MIM capacitors under different thicknesses and PDA temperature.
Fig. 3-3.    (a) C-V and (b) J-V characteristics of various Ni/TiO2/TaN MIM capacitors under different thicknesses.
Fig. 3-4.    C-V and J-V characteristics of Ni/ZrO2/TiN and TiN/ZrO2/TiN MIM capacitors with different upper TiN and Ni electrode.
Fig. 3-5.    (a) C-V characteristics of different Ni/TiO2/ZrO2/TiN and control Ni/ZrO2/TiN MIM capacitors. (b) J-V characteristics measured at 25 oC and (c) J-V characteristics measured at 125oC of different Ni/TiO2/ZrO2/TiN and control Ni/ZrO2/TiN MIM capacitors.
Fig. 3-6.    (a) The XRD spectra and (b) Cross-sectional TEM of TiO2(3nm)/ZrO2(6.5nm)/TiN structure.
Fig. 3-7.    The AFM of TiO2(3nm)/ZrO2(6.5nm)/TiN structure.
Fig. 3-8.    (a) Measured and simulated ln(J)-E1/2 and (b) the ln(J/T2)-E1/2 plots of Ni/TiO2(3nm)/ZrO2(6.5nm)/TiN and control Ni/ZrO2(8nm)/TiN MIM capacitors.
Fig. 3-9.    (a) delta-C/C-V of different Ni/TiO2/ZrO2/TiN and control Ni/ZrO2/TiN MIM capacitors and (b) Quadratic voltage coefficient of delta-C/C-V vs. 1/C and CET plot.
Fig. 3-10.(a) delta-C/C as a function of stress time and (b) delta-C/C after 10 years span as a function of stress voltage for different Ni/TiO2/ZrO2/TiN and control Ni/ZrO2/TiN MIM capacitors.

Chapter 4  Compare the Performance of Charge-Trapping Memory with Different Single and Double Quantum Barriers
Fig. 4-1.    Band diagram of (a) [Metal-gate]-[High-□ barrier]-[Trapping Layer]-SiO2-Si MONOS non volatile memory device and (b) [Metal-gate]-[High-k top barrier 1-High-□ top barrier 2]-[Trapping Layer]-[High-k bottom barrier 2-SiO2]-Si double-quantum-barrier charge-trapping NVM.
Fig. 4-2.    C-V hysteresis for double-quantum-barrier device, showing a large Vfb shift.
Fig. 4-3.    Comparison of (a) program and (b) erase characteristics between single- and double-quantum-barrier devices under different voltages & times. For the erase both devices were initially programmed at 9 V for 100 us
Fig. 4-4.    Device retention characteristics (a) single- and (b) double-quantum-barrier charge-trapping devices at different temperature.
Fig. 4-5.    Comparison of (a) endurance characteristics and (b) retention characteristics after 103 P/E cycling of single- and double-quantum-barrier devices.
Fig. 4-6.    Id-Vg characteristics of (a) single- and (b) double-quantum-barrier devices after cycling.
Fig. 4-7.    Comparison of the interface trap density (Dit) for single- and double-barrier devices after P/E cycling.

Chapter 5  Good Retention and Fast Erase Novel Charge-Trapping-Engineered Non-Volatile Memory with Scaled Si3N4
Fig. 5-1.    (a)Energy band diagram of a MONOS NVM device. The using deep trapping high-k□layer can improve stored charges retention beyond Si3N4. (b) Schematic band alignment of various metal-nitride and metal- oxide-nitride trapping layers to the oxide barrier and Si channel.
Fig. 5-2.    Schematic energy band diagram of (a) conventional MONOS, (b)  double-barrier, double-tunnel and single-Si3N4 charge-trapping flash (CTF) memory (control), and (c) charge-trapping-engineered flash (CTEF) non-volatile memory with shallow- and deep- trapping layers and additional delta-EC in trapping layer to double-tunnel layers (this work).
Fig. 5-3.    (a) Jg-Vg characteristics of CTEF devices at 25, 85, and 150oC. (b) C-V hysteresis of CTEF devices.
Fig. 5-4.    (a) Program and (b) erase characteristics as functions of voltage and time for CTEF devices. For erase, the device was initially programmed at 16 V for 100 us.
Fig. 5-5.    (a) Program and (b) erase characteristics as functions of voltage and time for control CTF devices. For erase, the device was initially programmed at 16 V for 100 us.
Fig. 5-6.    Retention characteristics of CTEF devices at (a) 25oC, (b) 85oC, and 150oC.
Fig. 5-7.    Retention characteristics of CTF devices at 25, 85, and 150oC.
Fig. 5-8.    Retention characteristics of CTEF and CTF devices at 150oC. For comparison, the CTEF wrote at nearly the same initial memory window is shown.
Fig. 5-9.    (a) Endurance characteristics of CTEF devices. (b) 1K cycled retention characteristics of CTEF and control CTF devices.



Table Captions

Chapter 2  Low  Threshold  Voltage [TaN-TaN/Ir]/LaTiO n- and p-MOSFETs Incorporating Low-Temperature-Formed      Shallow Junctions
Table 2-1.Comparison of device integrity data for various metal-gate/high-k n- and   p-MOSFETs.

Chapter 3  High k and High Density Ni/ZrO2/TiN and Ni/TiO2/ZrO2/TiN MIM Capacitors for Analog and Memory Applications
Table 3-1.Comparison of device integrity data for various MIM capacitors.

Chapter 5  Good Retention and Fast Erase Novel Charge-Trapping-Engineered Non-Volatile Memory with Scaled Si3N4
Table 5-1.Comparisons of P/E voltage, speed, initial Vth, extrapolated for 10-year retention at 85 and 150oC and endurance.

                                

References

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[1.17] D. S. Yu , A. Chin, C. C. Liao, C. F. Lee, C. F. Cheng, M. F. Li, Won Jong Yoo, and S. P. McAlister, “3D Metal-Gate/High-κ/GOI CMOSFETs on 1-Poly-6-Metal 0.18-μm Si Devices,” IEEE Electron Device Lett. 26, Feb. 2005, pp. 118-120.
[1.18] X. P. Wang, C. Shen, Ming-Fu Li, H.Y. Yu, Yiyang Sun, Y. P. Feng, Andy Lim, Hwang Wan Sik, Albert Chin, Y. C. Yeo, Patrick Lo, and D.L. Kwong,” Dual Metal Gates with Band-Edge Work Functions on Novel HfLaO High-κ Gate Dielectric,” in Symp. on VLSI Technology, 2006, pp. 12-13.
[1.19] J. H. Lee, H. Zhong, Y.-S. Suh, G. Heuss, J. Gurganus, B. Chen, and V. Misra,” Tunable work function dual metal gate technology for bulk and nonbulk CMOS,” in IEDM Tech. Dig., 2002, pp. 359-362.
[1.20] H. Y. Yu, M. F. Li, and D.L. Kwong,” Thermally Robust HfN Metal as a Promising Gate Electrode for Advanced MOS Device Application,” IEEE Transactions on Electron Devices, vol. 51, Apr., 2004, pp. 609-615.
[1.21] D. S. Yu, A. Chin, C. H. Wu, M.-F. Li, C. Zhu, S. J. Wang, W. J. Yoo, B. F. Hung and S. P. McAlister, “Lanthanide and Ir-based dual metal-gate/HfAlON CMOS with large work-function difference,” in IEDM Tech. Dig., 2005, pp. 649-652.
[1.22] C. H. Lee, K. I. Choi, M. K. Cho, Y. H. Song, K. C. Park, and K. Kim, “A novel SONOS structure of SiO2/SiN/Al2O3 with TaN metal gate for multi-giga bit flash memories,” in IEDM Tech. Dig., pp. 613-616, 2003.
[1.23] C.-M. Hung, Y.-C. Ho, I.-C. Wu, and K. O, “High-Q capacitors implemented in a CMOS process for low-power wireless applications,” in IEEE MTT-S Int. Microwave Symp. Dig., 1998, pp. 505-511.
[1.24] J. A. Babcock, S. G. Balster, A. Pinto, C. Dirnecker, P. Steinmann, R. Jumpertz, and B. El-Kareh, “Analog characteristics of metal-insulator-metal capacitors using PECVD nitride dielectrics,” IEEE Electron Device Lett., vol. 22, pp. 230-232, May 2001.
[1.25] C. H. Ng, K. W. Chew, and S. F. Chu, “Characterization and comparison of PECVD silicon nitride and silicon oxynitride dielectric for MIM capacitors,” IEEE Electron Device Lett., vol. 24, pp. 506-508, Aug. 2003.
[1.26] L. Y. Tu, H. L. Lin, L. L. Chao, D. Wu, C. S. Tsai, C. Wang, C. F. Huang, C. H. Lin, and J. Sun, “Characterization and comparison of high-κ metal–insulator–metal (MIM) capacitors in 0.13 μm Cu BEOL for mixed-mode and RF applications,” in Symp. VLSI Tech. Dig., 2003, pp. 79-80.
[1.27] Z. Chen, L. Guo, M. Yu, and Y. Zhang, “A study of MIMIM on-chip capacitor using Cu/SiO2 interconnect technology,” IEEE Microwave and Wireless Components Lett., vol. 12, pp. 246-248, July 2002.
[1.28] C. Zhu, H. Hu, X. Yu, S. J. Kim, A. Chin, M. F. Li, B. J. Cho, and D. L. Kwong, “Voltage and temperature dependence of capacitance of high-κ HfO2 MIM capacitors: a unified understanding and prediction,” in IEDM Tech. Dig., 2003, pp. 879-882.
[1.29] S. J. Kim, B. J. Cho, M.-F. Li, C. Zhu, A. Chin, and D. L. Kwong, “HfO2 and lanthanide-doped HfO2 MIM capacitors for RF/mixed IC applications,” in Symp. on VLSI Tech. Dig., 2003, pp. 77-78.
[1.30] S. J. Kim, B. J. Cho, S. J. Ding, M.-F. Li, M. B. Yu, C. Zhu, A. Chin, and D.-L. Kwong, “Engineering of voltage nonlinearity in high-□ MIM capacitor for analog/mixed-Signal ICs,” in Symp. on VLSI Tech. Dig., 2004, pp. 218-219.
[1.31] H. Hu, S. J. Ding, H. F. Lim, C. Zhu, M.F. Li, S.J. Kim, X. F. Yu, J. H. Chen, Y. F. Yong, B. J. Cho, D.S.H. Chan, S. C. Rustagi, M. B. Yu, C. H. Tung, A. Du, D. My, P. D. Fu, A. Chin, and D. L. Kwong, “High performance HfO2-Al2O3 laminate MIM capacitors by ALD for RF and mixed signal IC applications,” in IEDM Tech. Dig., 2003, pp. 879-882.
[1.32] S. J. Kim, B. J. Cho, M.-F. Li, C. Zhu, A. Chin, and D. L. Kwong, “Lanthanide (Tb)-doped HfO2 for high density MIM Capacitors,” IEEE Electron Device Lett., vol. 24, pp. 442-444, July 2003.
[1.33] T. Ishikawa, D. Kodama, Y. Matsui, M. Hiratani, T. Furusawa, and D. Hisamoto, “High-capacitance Cu/Ta2O5/Cu MIM structure for SoC applications featuring a single-mask add-on process, in IEDM Tech. Dig., 2002, pp. 940-942.
[1.34] S. B. Chen, J. H. Lai, K. T. Chan, A. Chin, J. C. Hsieh, and J. Liu, “Frequency-dependent capacitance reduction in high-k AlTiOx and Al2O3 gate dielectrics from IF to RF frequency range,” IEEE Electron Device Lett., vol. 23, pp. 203-205, Apr. 2002.
[1.35] C. H. Huang, M.Y. Yang, A. Chin, C. X. Zhu, M. F. Li, and D. L. Kwong, “High density RF MIM capacitors using High-κ AlTaOx dielectrics,” in IEEE MTT-S Int. Microwave Symp. Dig., 2003, vol. 1, pp. 507-510.
[1.36] M. Y. Yang, C. H. Huang, A. Chin, C. Zhu, B. J. Cho, M. F. Li, and D. L. Kwong, “Very high density RF MIM capacitors (17fF/μm2) using high-κ Al2O3 doped Ta2O5 dielectrics,” IEEE Microwave & Wireless Comp. Lett., vol. 13, pp. 431-433, Oct. 2003.
[1.37] S. J. Kim, B. J. Cho, M. B. Yu, M.-F. Li, Y.-Z. Xiong, C. Zhu, A. Chin, and D. L. Kwong, “High capacitance density (>17fF/μm2) Nb2O5 – based MIM capacitors for future RF IC applications,” in Symp. on VLSI Tech. Dig., 2005, pp. 56-57.
[1.38] White, M.H.; Yang Yang; Ansha Purwar; French, M.L., “A low voltage SONOS nonvolatile semiconductor memory technology”, IEEE Transactions on Components, Packaging and Manufacturing Technology Part A, Vol. 20, pp.190-195, 1997.
[1.39] Zhu, W.; Ma, T.P.; Tamagawa, T.; Di, Y.; Kim, J.; Carruthers, R.; Gibson, M.; Furukawa, T.; “HfO2 and HfAlO for CMOS: thermal stability and current transport “, International Electron Devices Meeting Technical Digest, pp. 20.4.1 -20.4.4, 2001.
[1.40] T. Yamaguchi, H. Satake, N. Fukushima and A. Toriumi, “ Band Diagram and Carrier Conduction Mechanism in ZrO2/Zr-silicate/Si MIS Structure Fabricated by Pulsed-laser-ablation Deposition”, IEDM Technical Digest, pp.19-22, 2000.
[1.41] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C.-H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks , R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. McIntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad , L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren0, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, and K. Zawadzki, “A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging,” in IEDM Tech. Dig., 2007, pp. 247-250.
[1.42] K. C. Chiang, C. C. Huang, Albert Chin, W. J. Chen, H. L. Kao, M. Hong, and J. Kwo, “High performance micro-crystallized TaN/SrTiO3/TaN capacitors for analog and RF applications,” in Symp. on VLSI Tech. Dig., 2006, pp.126-127.
[1.43] S. M. Sze, Physics of Semiconductor Devices, John Wiley & Sons, Murray Hill, New Jersey,1981.

Chapter 2:
[2.1] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C.-H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks , R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. McIntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad , L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren0, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, and K. Zawadzki, “A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging,” in IEDM Tech. Dig., 2007, pp. 247-250.
[2.2] V. S. Chang, L.-A. Ragnarsson, G. Pourtois, R. O’Connor, C. Adelmann, S. Van Elshocht, A. Delabie, J. Swerts, N. Van der Heyden, T. Conard, H.-J. Cho, A. Akheyar, R. Mitsuhashi, T. Witters, B. J. O’Sullivan, L. Pantisano, E. Rohr, P. Lehnen, S. Kubicek, T. Schram, S. De Gendt, P. P. Absil, and S. Biesemans, “A Dy2O3-capped HfO2 Dielectric and TaCx-based Metals Enabling Low-Vt Single-Metal-Single-Dielectric Gate Stack,” in IEDM Tech. Dig., 2007, pp. 535-538.
[2.3] T. Hoffmann, A. Veloso, A. Lauwers, H. Yu, H. Tigelaar, M. Van Dal, T. Chiarella, C. Kerner, T. Kauerauf, A. Shickova, R. Mitsuhashi, I. Satoru, M. Niwa, A. Rothschild, B. Froment, J. Ramos, A. Nackaerts, M. Rosmeulen, S. Brus, C. Vrancken, P. P. Absil, M. Jurczak, S. Biesemans and J. A. Kittl, “Ni-based FUSI gates: CMOS Integration for 45nm node and beyond,” in IEDM Tech. Dig., 2006, pp. 269-272.
[2.4] M. Kadoshima, T. Matsuki, M. Sato, T. Aminaka, E. Kurosawa, A. Ohta, H. Yoshinaga, S. Miyazaki, K. Shiraishi, K. Yamabe, K. Yamada, T. Aoyama, Y. Nara, and Y. Ohji, “Practical dual-metal-gate dual-high-k CMOS integration technology for hp 32 nm LSTP utilizing process-friendly TiAlN metal gate,” in IEDM Tech. Dig., 2007, pp. 531-534.
[2.5] K. Takahashi, K. Manabe, T. Ikarashi, N. Ikarashi, T. Hase, T. Yoshihara, H. Watanabe, T. Tatsumi, and Y. Mochizuki, “Dual workfunction Ni-silicide/HfSiON gate stacks by phase-controlled full-silicidation (PC-FUSI) technique for 45nm-node LSTP and LOP devices,” in IEDM Tech. Dig., 2004, pp. 91-94.
[2.6] C. F. Cheng, C. H. Wu, N. C. Su, S. J. Wang, S. P. McAlister and Albert Chin,
“ Very low Vt [Ir-Hf]/HfLaO CMOS using novel self-aligned low temperature shallow junctions,” in IEDM Tech. Dig., 2007, pp. 333-336.
[2.7] C. C. Liao, Albert Chin, N. C. Su, M.-F. Li, and S. J. Wang, “Low Vt gate-first Al/TaN/[Ir3Si-HfSi2-x]/HfLaON CMOS using simple process,” in Symp. on VLSI Tech. Dig., 2008, pp. 190-191.
[2.8] D. S. Yu, Albert Chin, C. H. Wu, M.-F. Li, C. Zhu, S. J. Wang, W. J. Yoo, B. F. Hung and S. P. McAlister, “Lanthanide and Ir-based dual metal-gate/HfAlON CMOS with large work-function difference,” in IEDM Tech. Dig., 2005, pp. 649-652.
[2.9] C. H. Wu, D. S. Yu, Albert Chin, S. J. Wang, M.-F. Li, C. Zhu, B. F. Hung, and S. P. McAlister, “High work function IrxSi gates on HfAlON p-MOSFETs,” IEEE Electron Device Lett. 27, no. 2, pp. 90-92, 2006.
[2.10] X. P. Wang, C. Shen, M.-F. Li, H. Y. Yu, Y. Sun, Y. P. Feng, A. Lim, H. W. Sik, A. Chin, Y. C. Yeo, P. Lo, and D. L. Kwong, “Dual metal gates with band-edge work functions on novel HfLaO high-κ gate dielectric,” in Symp on VLSI Tech. Dig., 2006, pp. 12-13.
[2.11] C. H. Wu, B. F. Hung, Albert Chin, S. J. Wang, X. P. Wang, M.-F. Li, C. Zhu, Y. Jin, H. J. Tao, S. C. Chen, and M. S. Liang, “High temperature stable [Ir3Si-TaN]/HfLaON CMOS with large work-function difference,” in IEDM Tech. Dig., 2006, pp. 617-620.
[2.12] B. F. Hung, C. H. Wu, Albert Chin, S. J. Wang, F. Y. Yen, Y. T. Hou, Y. Jin, H. J. Tao, S. C. Chen, and M. S. Liang, “High temperature stable IrxSi gates with high work function on HfSiON p-MOSFETs,” IEEE Trans. Electron Device, vol. 54, pp. 257-261, Feb. 2007.
[2.13] M. Takahashi, A. Ogawa, A. Hirano, Y. Kamimuta, Y. Watanabe, K. Iwamoto, S. Migita, N. Yasuda, H. Ota, T. Nabatame and A. Toriumi, “Gate-first processed FUSI/HfO2/HfSiOx/Si MOSFETs with EOT=0.5 nm- interfacial layer formation by cycle-by-cycle deposition and annealing,” in IEDM Tech. Dig., 2007, pp. 523-526.
[2.14] H.-H. Tseng, C. C. Capasso, J. K. Schaeffer, E. A. Hebert, P. J. Tobin, D. C. Gilmer, D. Triyoso, M. E. Ramón, S. Kalpat, E. Luckowski, W. J. Taylor, Y. Jeon, O. Adetutu, R. I. Hegde, R. Noble, M. Jahanbani, C. El Chemali, and B. E. White, “Improved short channel device characteristics with stress relieved pre-oxide (SRPO) and a novel tantalum carbon alloy metal gate/HfO2 stack,” in IEDM Tech. Dig., 2004, pp. 821-824.
[2.15] T. Nabatame, M. Kadoshima, K. Iwamoto, N. Mise, S. Migita, M. Ohno, H. Ota, N. Yasuda, A. Ogawa, K. Tominaga, H. Satake, and A. Toriumi, “Partial silicides technology for tunable work function electrodes on high-k gate dielectrics- fermi level pinning controlled PtSix for HfOx(N) pMOSFET,” in IEDM Tech. Dig., 2004, pp.83-86.
[2.16] X. Yu, M. Yu and C. Zhu, “Advanced HfTaON/SiO2 gate stack with high mobility and low leakage current for low –standby-power application,” IEEE Electron Device Lett. Vol. 27, no. 6, pp. 498-501, 2006.
[2.17] P. F. Hsu, Y. T. Hou, F. Y. Yen, V. S. Chang, P. S. Lim, C. L. Hung, L.G. Yao, J. C. Jiang, H. J. Lin, J. M. Chiou, K. M. Yin, J. J. Lee, R. L. Hwang, Y. Jin, S. M. Chang, H. J. Tao, S. C. Chen, M. S. Liang, and T. P. Ma, “Advanced dual metal gate MOSFETs with high-k dielectric for CMOS application,” in Symp. VLSI Tech. Dig., 2006, pp. 14-15.
[2.18] H. Y. Yu, R. Singanamalla, K. Opsomer, E. Augendre, E. Simoen, J.A. Kittl, S. Kubicek, S. Severi, X.P. Shi, S. Brus, C. Zhao, J.F. de Marneffe, S. Locorotondo, D. Shamiryan, M. Van Dal, A. Veloso, A. Lauwers, M.Niwa, K. Maex, K. D. Meyer, P. Absi, M. Jurczak, and S. Biesemans, “Demonstration of Ni Fully GermanoSilicide as a pFET Gate Electrode Candidate on HfSiON,” in IEDM Tech. Dig., 2005, pp.653-656.
[2.19] S. Datta, G. Dewey, M. Doczy, B.S. Doyle, B. Jin, J. Kavalieros, R. Kotlyar, M. Metz, N. Zelick and R. Chau, “High Mobility Si/SiGe strained channel MOS transistors with HfO2/TiN gate stack,” in IEDM Tech. Dig., 2003, pp. 653-656.
[2.20] W. Tsai, L.-Å Ragnarsson, L. Pantisano, P.J. Chen, B. Onsia, T. Schram, E. Cartier, A. Kerber, E. Young, M. Caymax ,S. De Gendt, and M. Heyns, “Performance comparison of sub 1 nm sputtered TiN/HfO2 nMOS and pMOSFETs,” in IEDM Tech. Dig., 2003, pp. 311-314.
[2.21] K. C. Chiang, Albert Chin, C. H. Lai, W. J. Chen, C. F. Cheng, B. F. Hung, and C. C. Liao, “Very high □ and high density TiTaO MIM capacitors for analog and RF applications,” in Symp. on VLSI Tech. Dig., 2005, pp. 62-63.
[2.22] C. Y. Lin, W. J. Chen, C. H. Lai, A. Chin, and J. Liu, “Formation of Ni germano-silicide on single crystalline Si0.3Ge0.7/Si,” IEEE Electron Device Lett. vol. 23, pp. 464-466, Aug. 2002.
[2.23] S. H. Lin, S. L. Liu, F. S. Yeh, and Albert Chin, “Low Vt TaN/HfLaO n-MOSFETs using low temperature formed source-drain junctions,” IEEE Electron Device Lett., vol. 30, pp. 75-77, Jan. 2009.
[2.24] A. Kinoshita, Y. Tsuchiya, A. Yagishita, K. Uchida, and J. Koga, “Solution for high-performance Schottky-source/drain MOSFETs: Schottky barrier height engineering with dopant segregation technique,” in Symp. VLSI Tech. Dig., 2004, pp. 168-169.

Chapter 3:
[3.1] The International Technology Roadmap for Semiconductors: Semicond. Ind. Assoc., Process Integration, Devices, and Structures Chapter, pp. 30-33, 2007, Available: www.itrs.net.
[3.2] C.-M. Hung, Y.-C. Ho, I.-C. Wu, and K. O, “High-Q capacitors implemented in a CMOS process for low-power wireless applications,” in IEEE MTT-S Int. Microwave Symp. Dig., 1998, pp. 505-511.
[3.3] J. A. Babcock, S. G. Balster, A. Pinto, C. Dirnecker, P. Steinmann, R. Jumpertz, and B. El-Kareh, “Analog characteristics of metal-insulator-metal capacitors using PECVD nitride dielectrics,” IEEE Electron Device Lett., vol. 22, pp. 230-232, May 2001.
[3.4] C. H. Ng, K. W. Chew, and S. F. Chu, “Characterization and comparison of PECVD silicon nitride and silicon oxynitride dielectric for MIM capacitors,” IEEE Electron Device Lett., vol. 24, pp. 506-508, Aug. 2003.
[3.5] T. Ishikawa, D. Kodama, Y. Matsui, M. Hiratani, T. Furusawa, and D. Hisamoto, “High-capacitance Cu/Ta2O5/Cu MIM structure for SoC applications featuring a single-mask add-on process, in IEDM Tech. Dig., 2002, pp. 940-942.
[3.6] S. B. Chen, J. H. Lai, A. Chin, J. C. Hsieh, and J. Liu, “High density MIM capacitors using Al2O3 and AlTiOx dielectrics,” IEEE Electron Device Lett. vol. 23, pp. 185-188, April 2002.
[3.7] S. B. Chen, J. H. Lai, K. T. Chan, A. Chin, J. C. Hsieh, and J. Liu, “Frequency-dependent capacitance reduction in high-k AlTiOx and Al2O3 gate dielectrics from IF to RF frequency range,” IEEE Electron Device Lett., vol. 23, pp. 203-205, April 2002.
[3.8] X. Yu, C. Zhu, H. Hu, A. Chin, M. F. Li, B. J. Cho, D.-L. Kwong, P. D. Foo, and M. B. Yu,” A high-density MIM capacitor (13fF/μm2) using ALD HfO2 dielectrics,” IEEE Electron Device Lett., vol. 24, pp. 63-65, Feb. 2003.
[3.9] H. Hu, S. J. Ding, H. F. Lim, C. Zhu, M.F. Li, S.J. Kim, X. F. Yu, J. H. Chen, Y. F. Yong, B. J. Cho, D.S.H. Chan, S. C. Rustagi, M. B. Yu, C. H. Tung, A. Du, D. My, P. D. Fu, A. Chin, and D. L. Kwong, “High performance HfO2-Al2O3 laminate MIM capacitors by ALD for RF and mixed signal IC applications,” in IEDM Tech. Dig., 2003, pp. 379-382.
[3.10] S. J. Kim, B. J. Cho, M.-F. Li, C. Zhu, A. Chin, and D. L. Kwong, “HfO2 and Lanthanide-doped HfO2 MIM capacitors for RF/mixed IC applications,” in Symp. on VLSI Tech. Dig., 2003, pp. 77-78.
[3.11] S. Y. Lee, H. Kim, P. C. McIntyre, K. C. Saraswat, and J. S. Byun, “Atomic layer deposition of ZrO2 on W for metal–insulator–metal capacitor application,” Appl. Phys. Lett., vol. 82, pp. 2874-2876, 2003.
[3.12] Y. H. Wu, C. K. Kao, B. Y. Chen, Y. S. Lin, M. Y. Li, and H. C. Wu, “High density metal-insulator-metal capacitor based on ZrO2/Al2O3/ZrO2 laminate dielectric,” Appl. Phys. Lett., vol. 93, p. 033511, 2008.
[3.13] S. J. Kim, B. J. Cho, M. B. Yu, M.-F. Li, Y.-Z. Xiong, C. Zhu, A. Chin, and D. L. Kwong, “High capacitance density (>17fF/μm2) Nb2O5 – based MIM capacitors for future RF IC applications,” in Symp. on VLSI Tech. Dig., 2005, pp. 56-57.
[3.14] K. C. Chiang, Albert Chin, C. H. Lai, W. J. Chen, C. F. Cheng, B. F. Hung, and C. C. Liao, “Very high-κ and high density TiTaO MIM capacitors for analog and RF applications,” in Symp. on VLSI Tech. Dig., 2005, pp. 62-63.
[3.15] K. C. Chiang, C. H. Lai, Albert Chin, T. J. Wang, H. F. Chiu, J. R. Chen, S. P. McAlister, and C. C. Chi, “Very high density (23fF/μm2) RF MIM capacitors using high-κ TiTaO as the dielectric,” IEEE Electron Device Lett., vol. 26, pp. 728-730, October 2005.
[3.16] C. H. Cheng, H. C. Pan, H. J. Yang, C. N. Hsiao, C. P. Chou, S. P. McAlister, and Albert Chin, “Improved high-temperature leakage in high-density MIM Capacitors by using a TiLaO dielectric and an Ir electrode,” IEEE Electron Device Lett., vol. 28, pp. 1095-1097, Dec. 2007.
[3.17] K. C. Chiang, C. C. Huang, Albert Chin, W. J. Chen, H. L. Kao, M. Hong, and J. Kwo, “High performance micro-crystallized TaN/SrTiO3/TaN capacitors for analog and RF applications,” in Symp. on VLSI Tech. Dig., 2006, pp.126-127.
[3.18] K. C. Chiang, C. C. Huang, Albert Chin, G. L. Chen, W. J. Chen, Y. H. Wu, Albert Chin, S. P. McAlister, “High performance SrTiO3 metal-insulator-metal capacitors for analog applications,” IEEE Trans. Electron Devices, vol 53, pp.2312-2319, September 2006.
[3.19] K. C. Chiang, C. H. Cheng, H. C. Pan, C. N. Hsiao, C. P. Chou, Albert Chin and H. L. Hwang, “High-Temperature leakage improvement in metal-insulator-metal capacitors by work-function tuning” IEEE Electron Device Lett., vol. 28, pp. 235-237, March 2007.
[3.20] C. H. Cheng, S. H. Lin, K. Y. Jhou, W. J. Chen, C. P. Chou, F. S. Yeh, J. Hu, M. Hwang, T. Arikado, S. P. McAlister, and Albert Chin, “The 300oC-Processed High Density TiO2 MIM Capacitors with Low Leakage Current,” IEEE Electron Device Lett., vol. 29, pp. 845-847, Aug. 2008.
[3.21] J Robertson, “Band offsets of wide-band-gap oxides and implications for future electron devices,” J Vac Sci Technol B, vol. 18, pp. 1785-1791, May 2000.
[3.22] K. C. Chiang, C. H. Cheng, K. Y. Jhou, H. C. Pan and C. N. Hsiao, C. P. Chou, S. P. McAlister, Albert Chin, and H. L. Hwang, “Use of a High Work-Function Ni Electrode Improved the Stress Reliability of Analog SrTiO3 Metal-Insulator-Metal Capacitors,” IEEE Electron Device Lett., vol. 28, pp. 694-696, Aug. 2007.

Chapter 4:
[4.1] S.-I. Minami and Y. Kamigaki, “A novel MONOS nonvolatile memory device ensuring 10-year data retention after 10 erase/write cycles, ”IEEE Trans. Electron Devices, vol. 40, pp. 2011–2017, Nov. 1993.
[4.2] M. H. White, Y. Yang, A. Purwar, and M. L. French, “A low voltage SONOS nonvolatile semiconductor memory technology,” IEEE Trans. Compon., Packag., Manufact. Technol. A, vol. 20, no. 2, pp. 190–195, Jun. 1997.
[4.3] M. She, H. Takeuchi, and T.-J. King, “Improved SONOS-type flash memory using HfO as trapping layer,” in Proc. IEEE Nonvolatile Semi. Memory Workshop, 2003, pp. 53–55.
[4.4] C. H. Lee, K. I. Choi, M. K. Cho, Y. H. Song, K. C. Park, and K. Kim, “A novel SONOS structure of SiO2/SiN/Al2O3 with TaN metal gate for multi-giga bit flash memories,” in IEDM Tech. Dig., 2003, pp. 613-616.
[4.5] C. W. Oh, S. D. Suk, Y. K. Lee, S. K. Sung, J.-D. Choe, S.-Y. Lee, D. U. Choi, K. H. Yeo, M. S. Kim, S.-M. Kim, M. Li, S. H. Kim, E.-J. Yoon, D.-W. Kim, D. Park, K. Kim, and B.-I. Ryu, “Damascence gate FinFET SONOS memory implemented on bulk silicon wafer,” in IEDM Tech. Dig., 2004, pp. 893-896.
[4.6] M. Specht, R. Kommling, L. Dreeskornfeld, W. Weber, F. Hofmann, D. Alvarez, J. Kretz, R.J. Luyken, W. Rosner, H. Reisinger, E. Landgraf, T. Schulz, J. Hartwich, M. Stadele, V. Klandievski, E. Hartmann, and L. Risch, “Sub-40nm tri-gate charge trapping nonvolatile memory cells for high-density applications,” in Symp. on VLSI Tech. Dig., 2004, pp. 244-245.
[4.7] X. Wang, J. Liu, W. Bai, and D.-L. Kwong, “A novel MONOS-type nonvolatile memory using high-□ dielectrics for improved data retention and programming speed,” IEEE Trans. Electron Devices, vol. 51, pp. 597-602, April 2004.
[4.8] Y. N. Tan, W. K. Chim, W. K. Choi, M. S. Joo, T. H. Ng, and B. J. Cho, “High-□ HfAlO charge trapping layer in SONOS-type nonvolatile memory device for high speed operation,” in IEDM Tech. Dig., pp. 889-892, 2004.
[4.9] H. T. Lue, S. Y. Wang. E. K. Lai, Y. H. Shih, S. C. Lai, L. W. Yang, K. C. Chen, J. Ku, K. Y. Hsieh, R. Liu, and C. Y. Lu, “A bandgap engineered SONOS with excellent performance and reliability,” in IEDM Tech. Dig., 2005, pp. 555-558.
[4.10] C. H. Lai, Albert Chin, K. C. Chiang, W. J. Yoo, C. F. Cheng, S. P. McAlister, C. C. Chi, and P. Wu, “Novel SiO2/AlN/HfAlO/IrO2 memory with fast erase, large □Vth and good retention,” in Symp. on VLSI Tech. Dig., 2005, pp. 210-211.
[4.11] Albert Chin, C. C. Laio, K. C. Chiang, D. S. Yu, W. J. Yoo, G. S. Samudra, S. P. McAlister, and C. C. Chi, “Low voltage high speed SiO2/AlGaN/AlLaO3/TaN memory with good retention,” in IEDM Tech. Dig., 2005, pp. 165-168.
[4.12] C. H. Lai, Albert Chin, H. L. Kao, K. M. Chen, M. Hong, J. Kwo, and C. C. Chi, “Very Low voltage SiO2/HfON/HfAlO/TaN memory with fast speed and good retention,” in Symp. on VLSI Tech. Dig., 2006, pp. 54-55.
[4.13] K. H. Joo, C. R. Moon, S. N. Lee, X. Wang, J. K. Yang, I. S. Yeo, D. Lee, O. Nam, U. I. Chung, J. T. Moon, and B. I. Ryu, “Novel charge trap devices with NCBO trap layers for NVM or image sensor,” in IEDM Tech. Dig., 2006, pp. 979-982.
[4.14] S. H. Gu, T. Wang, W. P. Lu, Y. H. Ku, and C. Y. Lu, “Extraction of nitride trap density from stress induced leakage current in silicon-oxide-nitride-oxide-silicon flash memory,” Appl. Phys. Lett., vol. 89, pp. 163514, 2006.
[4.15] H. J. Yang, Albert Chin, W. J. Chen, C. F. Chen, W. L. Huang, I. J. Hsieh, and S. P. McAlister “A program-erasable high-□□Hf0.3N0.2O0.5 MIS capacitor with good retention” IEEE Electron Devices Lett., vol. 28, pp. 913-915, Oct. 2007.
[4.16] C. H. Wu, B. F. Hung, Albert Chin, S. J. Wang, X. P. Wang, M.-F. Li, C. Zhu, Y. Jin, H. J. Tao, S. C. Chen, and M. S. Liang “High temperature stable [Ir3Si-TaN]/HfLaON CMOS with large work-function difference,” in IEDM Tech. Dig., 2006, pp. 617-620.
[4.17] J Robertson, “Band offsets of wide-band-gap oxides and implications for future electron devices,” J Vac Sci Technol B, vol. 18, pp. 1785-1791, May 2000.
[4.18] H. Y. Yu, M. F. Li, B. J. Cho, C. C. Yeo and M. S. Joo, “Energy gap and band alignment for (HfO2)x(Al2O3)1-x on (100) Si,” Appl. Phys. Lett., vol. 81, pp. 376-378, July 2002.
[4.19] R. Ohba, Y. Mitani, N. Sugiyama and S. Fujita, “15 nm Planar bulk SONOS-type memory with double junction tunnel layers using sub-threshold slope control,” in IEDM. Tech. Dig., 2007, pp. 75-78.
[4.20] Y. Y. Liao, S. F. Horng, Y. W. Chang, T. C. Lu, K. C. Chen, T. Wang, C. Y. Lu, “Profiling of nitride-trap-energy distribution in SONOS flash memory by using a variable-amplitude low-frequency charge-pumping technique,” IEEE Electron Devices Lett., vol. 28, pp. 828-830, Sept. 2007.

Chapter 5:
[5.1] International Technology Roadmap for Semiconductors (ITRS), Process Integration, Devices & Structures (PIDS) Chapter, pp. 35-47, 2007. [Online]. Available: www.itrs.net
[5.2] S.-I. Minami and Y. Kamigaki, “A novel MONOS nonvolatile memory device ensuring 10-year data retention after 10 erase/write cycles, ”IEEE Trans. Electron Devices, vol. 40, pp. 2011–2017, Nov. 1993.
[5.3] M. H. White, Y. Yang, A. Purwar, and M. L. French, “A low voltage SONOS nonvolatile semiconductor memory technology,” IEEE Trans. Compon., Packag., Manufact. Technol. A, vol. 20, no. 2, pp. 190–195, Jun. 1997.
[5.4] M. She, H. Takeuchi, and T.-J. King, “Improved SONOS-type flash memory using HfO as trapping layer,” in Proc. IEEE Nonvolatile Semi. Memory Workshop, 2003, pp. 53–55.
[5.5] C. H. Lee, K. I. Choi, M. K. Cho, Y. H. Song, K. C. Park, and K. Kim, “A novel SONOS structure of SiO2/SiN/Al2O3 with TaN metal gate for multi-giga bit flash memeries,” in IEDM Tech. Dig., 2003, pp. 613-616.
[5.6] M. Specht, R. Kommling, L. Dreeskornfeld, W. Weber, F. Hofmann, D. Alvarez, J. Kretz, R.J. Luyken, W. Rosner, H. Reisinger, E. Landgraf, T. Schulz, J. Hartwich, M. Stadele, V. Klandievski, E. Hartmann, and L. Risch, “Sub-40nm tri-gate charge trapping nonvolatile memory cells for high-density applications,” in Symp. on VLSI Tech. Dig., 2004, pp. 244-245.
[5.7] C. W. Oh, S. D. Suk, Y. K. Lee, S. K. Sung, J.-D. Choe, S.-Y. Lee, D. U. Choi, K. H. Yeo, M. S. Kim, S.-M. Kim, M. Li, S. H. Kim, E.-J. Yoon, D.-W. Kim, D. Park, K. Kim, and B.-I. Ryu, “Damascence gate FinFET SONOS memory implemented on bulk silicon wafer,” in IEDM Tech. Dig., 2004, pp. 893-896.
[5.8] X. Wang, J. Liu, W. Bai, and D.-L. Kwong, “A novel MONOS-type nonvolatile memory using high-□ dielectrics for improved data retention and programming speed,” IEEE Trans. Electron Devices, vol. 51, pp. 597-602, April 2004.
[5.9] Y. N. Tan, W. K. Chim, W. K. Choi, M. S. Joo, T. H. Ng, and B. J. Cho, “High-□ HfAlO charge trapping layer in SONOS-type nonvolatile memory device for high speed operation,” in IEDM Tech. Dig., pp. 889-892, 2004.
[5.10] X. Wang and D.-L. Kwong, “A novel high-□□SONOS memory using TaN/Al2O3/Ta2O5/HfO2/Si structure for fast speed and long retention operation,” IEEE Trans. Electron Devices, vol. 53, pp. 78-82, January 2006.
[5.11] S. H. Gu, T. Wang, W. P. Lu, Y. H. Ku, and C. Y. Lu, “Extraction of nitride trap density from stress induced leakage current in silicon-oxide-nitride-oxide-silicon flash memory,” Appl. Phys. Lett., vol. 89, pp. 163514-163516, 2006.
[5.12] C. H. Lai, Albert Chin, K. C. Chiang, W. J. Yoo, C. F. Cheng, S. P. McAlister, C. C. Chi, and P. Wu, “Novel SiO2/AlN/HfAlO/IrO2 memory with fast erase, large □Vth and good retention,” in Symp. on VLSI Tech. Dig., 2005, pp. 210-211.
[5.13] Albert Chin, C. C. Laio, K. C. Chiang, D. S. Yu, W. J. Yoo, G. S. Samudra, S. P. McAlister, and C. C. Chi, “Low voltage high speed SiO2/AlGaN/AlLaO3/TaN memory with good retention,” in IEDM Tech. Dig., 2005, pp. 165-168.
[5.14] C. H. Lai, Albert Chin, H. L. Kao, K. M. Chen, M. Hong, J. Kwo, and C. C. Chi, “Very Low voltage SiO2/HfON/HfAlO/TaN memory with fast speed and good retention,” in Symp. on VLSI Tech. Dig., 2006, pp. 54-55.
[5.15] K. H. Joo, C. R. Moon, S. N. Lee, X. Wang, J. K. Yang, I. S. Yeo, D. Lee, O. Nam, U. I. Chung, J. T. Moon, and B. I. Ryu, “Novel charge trap devices with NCBO trap layers for NVM or image sensor,” in IEDM Tech. Dig., 2006, pp. 979–982.
[5.16] H. J. Yang, Albert Chin, S. H. Lin, F. S. Yeh, and S. P. McAlister, “Improved high temperature retention for charge-trapping memory by using double quantum barriers,” IEEE Electron Device Lett., vol. 29, pp. 386-388, April 2008.

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