本論文使用了Digilent公司的Zedboard 精簡指令集/可程式化邏輯閘陣列開發板，搭配配套的系統來協助感應器內運算晶片的使用開發與記憶體內運算晶片的量測。晶片完成設計並製作出成品後，會需要對應的訊號輸出入和配套的供電，甚至是需要進一步的量測與調整才能真正的開始使用。

經過分析晶片的供電需求我將供電需求歸納成4種狀況，並依據需求設計滿足諸如大電流、電壓等等對應的電路。

在本篇論文中使用了3種不同的供電電路來供給晶片電力，讓不同的電力需求能得到解決，並對應不同的訊號電位標準提供了解決的方案，致使訊號能順利的傳輸而不會出現訊號電位不匹配導致的誤判和錯誤。

供電解決方案我分別對應不同的使用環境設計了一般情況下使用的包含LM317晶片配套電路以供給1.25V $\sim$ 37V的供電；針對較低的電壓使用的基於LM358放大器設計的電壓隨耦器以供給1.25V以下的需求；還有針對需要隨使用調整電壓的基於AD5697R數位類比轉換器的電路來滿足可調電壓的需求。

本篇論文共為感應器內運算晶片與記憶體內運算晶片設計對應配套的系統。感應器內運算晶片因其可於感應器內直接做捲積運算，所以可以有效地降低功耗和減少需要使用的資料頻寬，但相應的其需求的控制訊號與定時器訊號也增加了，本論文設計的系統就透過Zedboard為其提供足夠的IO訊號和使用其撘載的FPGA產生足夠的定時器訊號輸出。而對應記憶體內運算晶片的配套系統，記憶體內運算晶片內電路的特性可以讓資料不需要傳輸到記憶體之外的運算單元就可以在內部完成捲積運算，但其資料的輸出入也會需要大量的IO，並且其工作點的設定將會影響到其運算結果的準確性，而本論文設計的系統可為其提供大量的IO，並對晶片和系統做訊號電位的匹配，滿足其對資料吞吐量的需求，並且系統中的數位類比轉換器也可以在操作中隨時調整供給的電壓值以確保資料結果的正確性。

In this paper, I use Zedboard, which is developed by Digilent Inc., and some other peripherals to form a chip testing and measurement system. A chip needs not only correspond signals but also power supply to operate correctly. Sometimes it even needs to be biasing to the accurate voltage in order to function well. I had design four types of voltage supply and two types of current supply circuits in this paper to match different kinds of usage and solve the unmatched-load voltage of signals problem. For voltage supply, I provide 1. the external 12V or 12V on FMC to provide the power for the whole testing system 2. LM317 circuit for voltage between 1.25V to 37V; 3. LM358 with voltage follower for voltage which is lower than 1.25V; 4. DAC AD5697R for voltage which has to been changed while operating. For current supply I provide 1. simply resistor as loading to generate the current 2. LM334 circuit for more accurate current.

In this paper, I totally design two testing system for compute in sensor chip and compute in memory chip. The compute in sensor chip can lower the power consumption and bandwidth occupy, but it requires more control signals and clock signals. The CIS system I designed with Zedboard can provide enough IO, and the FPGA on the board can generate as many as clock signals it needs. The computing circuit in compute in memory chip can do the convolution inside the chip, but it will require many IO signals. Besides, the chip I use is working at 1V, which will not match with Zedboard, so the testing system provides both FMC and PMOD connectors to meet the requirement of IO use and use voltage transducer to translate the signal between different voltage level. In addition, the DAC chip in the system can also adjust the voltage while the operation to remain the correction of the result.

[1] A. electronics marketing, “Zynq™ evaluation and development hardware
user’s guide,” tech. rep., 2014.
[2] T. Yamazaki, H. Katayama, A. N. Shuji Uehara, M. Kobayashi, S. Shida,
M. Odahara, K. Takamiya, Y. Hisamatsu, S. Matsumoto, L. Miyashita,
Y. Watanabe, T. Izawa1, Y. Muramatsu, and M. Ishikawa, “A 1ms highspeed vision chip with 3d-stacked 140gops column-parallel pes for spatiotemporal image processing,” in 2017 IEEE International Solid-State Circuits
Conference (ISSCC), 2017.
[3] K. Lee, S.-Y. P. Seokjun Park, J. Cho, and E. Yoon, “A 272.49 pj/pixel
cmos image sensor with embedded object detection and bio-inspired 2d optic
flow generation for nano-air-vehicle navigation,” in 2017 Symposium on VLSI
Circuits, 2017.
[4] X. Zhong, A. B. Qian Yu, C.-Y. Tsui, and M.-K. Law, “A 2pj/pixel/direction
mimo processing based cmos image sensor for omnidirectional local binary
pattern extraction and edge detection,” in 2018 IEEE Symposium on VLSI
Circuits, 2018.
[5] K. Bong, S. Choi, C. Kim, S. Kang, Y. Kim, and H.-J. Yoo, “A 0.62mw
ultra-low-power convolutional-neuralnetwork face-recognition processor and
a cis integrated with always-on haar-like face detector,” in 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017.
[6] T.-H. Hsu, Y.-K. Chen, T.-H. Wen, W.-C. Wei, Y.-R. Chen, F.-C. Chang,
R.-S. Liu, C.-C. Lo, K.-T. Tang, M.-F. Chang, and C.-C. Hsieh, “A 0.5v realtime computational cmos image sensor with programmable kernel for alwayson feature extraction,” in 2019 IEEE Asian Solid-State Circuits Conference
(A-SSCC), 2019.
[7] K. Ando, K. Ueyoshi, K. Orimo, H. Yonekawa, S. Sato, H. Nakahara,
S. Takamaeda-Yamazaki, M. Ikebe, T. Asai, T. Kuroda, Fellow, and M. Motomura, “Brein memory: A single-chip binary/ternary reconfigurable inmemory deep neural network accelerator achieving 1.4 tops at 0.6 w,” in
IEEE Journal of Solid-State Circuits, 2018.
[8] W.-S. Khwa, J.-J. Chen, J.-F. Li, X. Si, E.-Y. Yang, X. Sun, R. Liu, P.-Y.
Chen, Q. Li, S. Yu, and M.-F. Chang, “A 65nm 4kb algorithm-dependent
computing-inmemory sram unit-macro with 2.3ns and 55.8tops/w fully parallel product-sum operation for binary dnn edge processors,” in 2018 IEEE
International Solid - State Circuits Conference - (ISSCC), 2018
[9] J. Zhang, Z. Wang, and N. Verma, “In-memory computation of a machinelearning classifier in a standard 6t sram array,” in IEEE Journal of Solid-State
Circuits, 2017.
[10] S. K. Gonugondla, M. Kang, and N. Shanbhag, “A 42pj/decision 3.12tops/w
robust in-memory machine learning classifier with on-chip training,” in 2018
IEEE International Solid - State Circuits Conference - (ISSCC), 2018.
[11] S. Inc., “Vita 57.4 fmc+ extender application note,” tech. rep.
[12] D. Inc., “Digilent pmod™ interface specification 1.1.0,” tech. rep., 2017.
[13] J. S. S. T. ASSOCIATION, “1.0 v +/- 0.1 v (normal range) and 0.7 v - 1.1 v
(wide range) power supply voltage and interface standard for nonterminated
digital integrated circuits,” tech. rep., 2007.
[14] J. S. S. T. ASSOCIATION, “1.2 v +/- 0.1v (normal range) and 0.8 - 1.3 v
(wide range) power supply voltage and interface standard for nonterminated
digital integrated circuits,” tech. rep., 2007.
[15] J. S. S. T. ASSOCIATION, “1.5 v +/- 0.1 v (normal range) and 0.9 v –1.6 v
(wide range) power supply voltage and interface standard for nonterminated
digital integrated circuits,” tech. rep., 2007.
[16] J. S. S. T. ASSOCIATION, “1.8 v ± 0.15 v (normal range) and 1.2 v - 1.95 v
(wide range) power supply voltage and interface standard for nonterminated
digital integrated circuits,” tech. rep., 2006.
[17] J. S. S. T. ASSOCIATION, “2.5 v ± 0.2 v (normal range) and 1.8 v –2.7 v
(wide range) power supply voltage and interface standard for nonterminated
digital integrated circuits,” tech. rep., 2007.
[18] J. S. S. T. ASSOCIATION, “Interface standard for nominal 3 v/3.3 v supply
digital integrated circuits,” tech. rep., 2007.
[19] J. S. S. T. ASSOCIATION, “Gunning transceiver logic (gtl) low-level, high
speed interface standard for digital integrated circuits,” tech. rep., 2007.