隨著於超大型積體電路技術逐日進步，無論是以低功率消耗伴隨較低效能需求的設計或是高功率消耗追求高效能展現的設計，都逐漸地朝著可以設計出更低的功率消耗但卻能提升效能展現的目標邁進。在低功率的議題上，我們檢視了各種功率消耗的發生原因以及特徵以尋找多種低功耗技術來改善它。這些技術過去多被獨立提出，亦有許多技術未經過各層次的驗證，故我們經過評估與模擬，選擇了可行性且效能高的多種低功率技術進行研究，包括了能大幅改善動態功率消耗的時脈閘控技術、根據電路需求改變的選擇式多重臨界電壓互補式金屬氧化層半導體技術以及休眠電晶體的應用。為了從邏輯單元基底設流程著手，我們設計了多重臨界電壓標準元件庫，並且將其應用於現行的流程中，包含電路合成與自動佈局的執行。而標準元件庫的產生流程與資訊以及標準元件之設計要領也是我們為了針對元件設計仔細探討的部分。在過去一些有待改善的低功率技術，我們也提出了實現方法將低功率技術整合成晶片並予以驗證，其中又以模組分析與切割以及區塊佈局方式為重點。在最後模擬結果中，我們看到了各式低功率技術所帶來的成效，包括了改善整體動態功率消耗(3%)、降低待機狀態功率消耗(78%)以及減低漏電流效應(56%)，均符合我們所預期之目標。

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