這一篇論文將會介紹一種新的方法來實現並且建立出一個二次諧波的升頻混頻器。在選取這樣的二次諧波混頻器下，將會使我們取得一個架構上的優勢只需要使用一半射頻頻率的本地振盪頻率來實現所需要的射頻頻率。因為只需要一半的本地振盪頻率,因此可以降低在直接升頻系統中，一般升頻混頻器因為本地振盪端以及射頻端彼此之間的頻率過於靠近，所容易碰到的本地振盪功率混入(混入射頻端)的問題。在這樣的二次諧波混頻器的設計中，我們將會需要去使用到一組八個相位的頻率產生器，而這個頻率產生器將利用兩組多相位濾波器來實現。為了驗證這顆我們所設計的混頻器，我們製造了一個利用.18混合模式互補式金氧半二極體製程的實驗性的晶片。依據量測得到的結果，可以得到-8.05 dB的混頻器的功率放大，7.56 dBm的IIP3，使用了24.3 mW的功率能量，而這個晶片的面積為1.2mm× 1.7mm。
設計這個混頻器所碰到的另一個問題則是相位誤差的問題。這篇論文將介紹一種相位誤差偵測的方法與機制，利用這樣的方法來得知相位誤差量的大小。在這裡我們歸納了三個不同種類的相位誤差：差動放大對的使用所造成的導通時間上的誤差，I/Q的相位誤差問題，以及本地振盪端上面八個相位彼此間的誤差。只要在這個混頻器中加入互補式金氧半二極體的切換器，前兩種的相位誤差將能夠被偵測出來。

This thesis introduces a new technique for establishing an up-conversion sub-harmonic mixer. The choice of the sub-harmonic mixer takes advantage of only half RF frequency needed at the LO port. This characteristic eliminate the LO feed through problem because the frequency of LO is usually close to RF frequency for conventional up-conversion mixer in homodyne system. For this sub-harmonic mixer design, an octet phase generator is needed, which is realized by two poly-phase filters. To verify the designed mixer, an experimental chip is fabricated by 0.18μm mixed-mode CMOS technology. According to the measurement results, the mixer gain is -8.05 dB, IIP3 is 7.56 dBm, power consumption is 24.3 mW and the chip area is 1.2mm× 1.7mm.
Another problem for this mixer is the phase mismatch. This thesis introduces a phase error detection technique to know how much the phase error is. There are three phase error sources: differential duration error, I/Q phase error, and total LO octet phase error. By adding CMOS switches to the mixer, the first two error sources can be detected.

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