適用於無線感測器網路微處理器的動態頻率和電力的管理

簡易檢索 / 詳目顯示

回結果列表

研究生：	郭穎瑜 Ying-yu Kuo
論文名稱：	適用於無線感測器網路微處理器的動態頻率和電力的管理 Dynamic Frequency and Power Management for WSN Microcontroller
指導教授：	許雅三 Yarsun Hsu
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2006
畢業學年度：	94
語文別：	英文
論文頁數：	94
中文關鍵詞：	無線感測器網路、電力管理、指令、頻率、動態、微處理器
外文關鍵詞：	wireless sensor network, power management, instruction, frequency, dynamic, microcontroller
相關次數：	點閱：3 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

在無線感測網路中，電池的電量決定了一個無線感測網路的生命長短。所以想要使得無線感測網路發揮最大的功效，有效的管理電力絕對是不可缺少的。在我們所提出的「針對無線感測網路所設計的可動態管理頻率以及電力的微處理器」中，特別針對無線感測網路中電力的管理來做設計。
我們的微處理器有以下三種特色:
1. 根據不同的狀況自動切換操作頻率，利用動態頻率的切換做電力的管理。
2. 提供使用者一套相關的電力管理的指令集。
3. 利用指令的方式，讓使用者可以修改我們的微處理器的參數，讓這個微處裡器可以適用在各種不同的應用上。
我們設計的微處理器的內容主要為下列三項:
1. 對於使用者而言: 提供一套簡單明瞭的指令集，讓使用的人可以利用指令在微處理器的操作中切換操作頻率，或是利用指令來修改我們的微處理器的電力管理機制，使其適用於各種不同的省電的演算法。
2. 針對電池的電力而言: 根據電池電量的高低，有相對應的操作頻率。
3. 針對當感測網路需要處理資料時: 根據不同的忙碌程度，可自動變換操作頻率。若是為處理器閒置超過一定的時間，則關閉它。

In a wireless network, the battery power decides the operation duration of a Wireless Sensor Network (WSN). Therefore, it is critical how to effectively manage the power of a wireless sensor. We propose a ‘Dynamic Frequency and Power Management Microcontroller for Wireless Sensor Network’ to solve this problem.
There are three main characters of our microcontroller:
1. Dynamic change of operating frequency according to different constraints.
2. Provide the user the corresponding instructions to manage the power.
3. By giving instructions, our microcontroller is a customized one. (The user can modify the parameters of the microcontroller by giving instructions so that it can be used in various applications.
There are three main contents of our microcontroller:
1. For users: We provide a easy understood instruction set (We provide a set of simple and clear instructions.) The users can use these instructions to change the operation frequency when the microcontroller is in operation. The users can also modify the parameters of power management mechanism to suit different power saving algorithms.
2. For battery power: Different level of battery power has its corresponding operating frequency. The operating frequency corresponds to different battery power outputs.
3. For the network: The operating frequency automatically changes according to various levels of activeness. The operating frequency automatically changes according to the level of activeness of the network.

Contents

List of Figure
List of Table
Contents    i
List of Figure    i
List of Table    i
Chapter 1    1
Introduction    1
1-1    MOTIVATION    1
1-2 CONTRIBUTION    2
1-3 THESIS ORGANIZATION    3
Chapter 2    4
Clock Gating and the Analysis of Operating Frequency    4
2-1 CLOCK GATING    4
2-2 THE ANALYSIS OF THE INFLUENCE OF CLOCK ON THE CIRCUIT    5
2-3 THE CLASSIFICATION OF CLOCK GATING    7
2.3.1 Fine-grained vs. Coarse-grained    8
2-3.2 Central Clock Gating    9
2-3.3 Distributed Clock Gating    11
2-3.3a Unit Level Clock Gating    13
2-3.3b Flop Level Clock Gating    13
2-3.4 System Level    13
2-3.5 Register level    14
2-4 INTRODUCTION OF THE COMPONENTS OF CLOCK GATING    15
2-4.1 Combinational Gating Logic    16
2-4.1a AND Gate    17
2-4.1b NAND Gate    18
2-4.2 Latch Based Gating Level    19
Chapter 3    21
PIC16C57    21
3-1 THE INTRODUCTION OF PIC16C57 MICROCONTROLLER    21
3-1.1 Feature    22
3-2 ARCHITECTURE OVERVIEW    24
3-2.1 ALU    28
3-2.2 Special Function Register    30
3-2.2a Program Counter    31
3-2.2b I/O Ports    32
3-3 INSTRUCTION SET    32
Chapter 4    37
The Architecture and Circuit of Dynamic Frequency and Power Management Microcontroller    37
4-1 ARCHITECTURE OVERVIEW    37
4-2 SPECIAL FEATURES OF THE MCU    38
4-2.1Clock Generator    39
4-2.2 Dynamic Power Management    44
4-2.2a State    45
4-2.2b Dynamic Power Management FSM    47
4-2.2c Table    51
4-2.3 Special Purpose Register    51
4-2.3a Status Register    51
4-2.3d TMR0    55
4-2.4 Summary of Different Frequency Modes    56
4-3 INSTRUCTION SET SUMMARY    56
Chapter 5    69
Experimental result    69
5-1 DESIGN FLOW    69
5-2 SIMULATION RESULT    70
5-2.1 Functionality    70
5-2.2 Power Analysis    83
5-2.3 Synthesis Report    87
Chapter 6    88
Conclusion and Future Work    88
6-1 CONCLUSION    88
6-2 FUTURE WORK    88


List of Figures

FIGURE 2-2.1: Power Consumption of Various Sections of Intel740    6
FIGURE 2-2.2: Model of Sequential Machine    7
FIFURE 2-3.1: Clock Gating Mechanisms: (a)coarse grained vs. (b)fine grained.    9
FIGURE 2-3.2: Central Clock Gating    10
FIGURE 2-3.3: Distributed Clock Gating    12
FIGURE 2-3.4: Clock Gating From System View    14
FIGURE 2-3.5: Clock Gating Principle.    15
FIGURE 2-4.1: Four Classic Gates for Clock Gating    17
FIGURE 2-4.2: Illegal Timing (AND Gate)    18
FIGURE 2-4.3: Correct Timing (NAND Gate)    18
FIGURE 2-4.4: Latch Based Clock Gating    19
FIGURE 3-2.1: PIC16C5X Series Block Diagram    25
FIGURE 3-2.2: Example: Instruction Pipeline Flow    26
FIGURE 3-2.4 :PIC16C57 Register File Map    27
FIGURE 3-2.2: ALU    29
FIGURE 3-2.3: Special Function Register    30
FIGURE 3-2.4: Load of PC Branch Instructions    31
FIGURE 3-3.2:General Format for Instructions    35
FIGURE 4-1.1: Architecture Overview    38
FIGURE 4-2.3: Example2: The Undesired Clock Wave Result    42
FIGURE 4-2.4: Example3: The Undesired Clock Wave Result    43
FIGURE 4-2.4: The Waveform Generate from Our Clock Generator    44
FIGURE 4-2.6: Dynamic Power Management FSM    48
FIGURE 4-2.7: Status Register    53
FIGURE 4-2.8: Option Register    54
FIGURE 4-2.9: State Register    55
FIGURE 5-1: Design Flow    69
FIGURE 5-2.1: Dynamic Clock Switch Form CLK to CLK/2, CLK/4, CLK/8, CLK/16, CLK/32, CLK/64 and CLK/128    71
FIGURE 5-2.2: Dynamic Clock Switch Form CLK/2 to CLK, CLK/4, CLK/8, CLK/16, CLK/32, CLK/64 and CLK/128    72
FIGURE 5-2.3: Dynamic Clock Switch Form CLK/4 to CLK, CLK/2, CLK/4, CLK/8, CLK/16, CLK/32, CLK/64 and CLK/128    73
FIGURE 5-2.4: Dynamic Clock Switch Form CLK/8 to CLK, CLK/2, CLK/4, CLK/16, CLK/32, CLK/64 and CLK/128    74
FIGURE 5-2.5: Dynamic Clock Switch Form CLK/16 to CLK, CLK/2, CLK/4, CLK/8, CLK/32, CLK/64 and CLK/128    75
FIGURE 5-2.6: Dynamic Clock Switch Form CLK/32 to CLK, CLK/2, CLK/4, CLK/8, CLK/16, CLK/64 and CLK/128    76
FIGURE 5-2.7: Dynamic Clock Switch Form CLK/64 to CLK, CLK/2, CLK/4, CLK/8, CLK/16, CLK/32 and CLK/128    77
FIGURE 5-2.8: Dynamic Clock Switch Form CLK/128 to CLK, CLK/2, CLK/4, CLK/8, CLK/16, CLK/32 and CLK/64    78
FIGURE 5-2.9: Function Check after Gate-Level Simulation    78
FIGURE 5-2.17: the MCU without the dynamic power management runs at different frequencies    83
FIGURE 5-2.18: The MCU With and Without Dynamic Power Management in Always Idle Conditions    84
FIGURE 5-2.19: The MCU With and Without Dynamic Power Management in Always Busy Conditions    85
FIGURE 5-2.20: Different Asleep to Sleep Duraiton    85
FIGURE 5-2.21: Different Idle to Asleep Duration    86
FIGURE 5-2.22: Overhead Caused by the Added Power Management Mechanism    86

















List of Tables


TABLE 2-4.1: Active enable value and clock gate hold mode    16
TABLE 3-3.1:Opcode Field Descriptions    33
TABLE 3-3.3: Instruction Set Summary    36
TABLE 4-2.1: State Register Default Value    55
TABLE 4-2.2: Eight Frequencies Supported in Our Design    56
TABLE 4-3.1: Instruction Set    60
TABLE 5-2: Synthesis Area Report    87

                                

Reference
[1] Yan Luo, Jia Yu, Jun Yang, Laxmi Bhuyan, Low Power Network Processor Design Using Clock Gating, IEEE/ACM Design Automation Conference (DAC), Ahaheim, California, June 13-17, 2005
[2]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 6, JUNE 2001 715‘Gated Clock Routing for Low-PowerMicroprocessor Design’ Jaewon Oh and Massoud Pedram, Senior Member, IEEE
[3]. ‘Automatic Clock Gating for Power Reduction’ Zia Khan Gaurav Mehta Graphics Component Division Low Power Design Technology Intel Corporation 1900 Prairie City Road Folsom, California 95630, USA
[4]http://www.microchip.com/
[5] ‘Advanced Clock Gating with Power Compiler’,Wolfgang Embacher, Christian Bosch, Martin Embacher and Frank Trautmann
[6] PIC16C5X EPROM/ROM-based 8-bit CMOS microcontroller Series
[7] V. Raghunathan, C. Schurgers, S. Park, and M. B. Srivastava, "Energy aware wireless microsensor networks", IEEE Signal Processing Magazine, vol. 19, iss. 2, pp. 40--50, March 2002. Energy-Aware Wireless Microsensor Networks
[8] http://www.opencores.org/projects.cgi/web/minirisc/overview
[9] Rudolf Usselmann, Mini-risc core, Sep 2004
[10] Synopsys Prime Power, Design Compiler
[11] http://www.cic.org.tw/
[12] http://www.synopsys.com/
[13] 講義 PowerCompiler/PrimePower, 曾一鳴, Synopsys

全文公開日期本全文未授權公開 (校內網路)
全文公開日期本全文未授權公開 (校外網路)

簡易檢索 / 詳目顯示

相關論文