適用於IEEE 802.16-2004 實體層基頻處理,使用係數排列的低功率管線式正交分頻多工傳送機設計

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研究生：	范揚鈞 Yang-Chun Fan
論文名稱：	適用於IEEE 802.16-2004 實體層基頻處理,使用係數排列的低功率管線式正交分頻多工傳送機設計 A Coefficient Ordering based Low Power Pipelined OFDM Transmitter Design for IEEE 802.16-2004 Physical Layer Baseband
指導教授：	吳仁銘 Jen-Ming Wu
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 通訊工程研究所 Communications Engineering
論文出版年：	2005
畢業學年度：	93
語文別：	英文
論文頁數：	95
中文關鍵詞：	快速傅立葉轉換、正交分頻多工、傳輸機設計
外文關鍵詞：	OFDM, FFT, 802.16
相關次數：	點閱：1 下載：0
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中文摘要
IEEE802.16(無線都會網路又稱IEEE Wireless MAN 或是WiMAX)，設計成在地面上能夠提供數英哩內皆可用寬頻存取的都會網路，其傳輸的資料傳輸速率表現可以比擬IEEE802.11的無線區域網路系統，甚至可以跟cable, DSL, 或是T1能夠提供的表現不相上下。而在IEEE802.16-2004這個標準問世之後，使用OFDM(正交分頻多工技術)調變的技術，大大的降低了ISI，根據這一份標準，我將在論文當中介紹我所設計的符合標準的傳送機，包括了編碼增益相當高的迴旋碼編碼器，降低群體錯誤發生機率的交錯器設計，以及符合標準如何在資料當中加入Pilot訊號於子載波中，經過反快速傅立葉轉換到了時域上後再加入Cyclic Prefix完成傳送機的基頻處理，而在傳送機之中的核心就是反快速傅立葉轉換處理器，我也將介紹以一種變換係數的方法使得係數編碼交換行為大幅減少的管線式快速傅立葉轉換處理器，不同於以往的平行式快速傅立葉轉換處理器，我們使用了符合即時的管線式快速傅立葉轉換處理器，並且根據前人的研究將係數重排的概念用在這個較為龐大點數的處理器中，我也將會提出量化誤差以及有限長度字長對於快速傅立葉轉換的影響，傳送機中唯一的雜訊來源就是量化雜訊，我也會提出一個符合標準的字元長度的量化雜訊訊雜比的比較，最後我們將這些設計以硬體描述語言撰寫(Verilog)之後，運用QUARTUS的軟體以及FPGA 實驗板，將我們的設計具體呈現出來，建立一個平台以供後人修改或是增加新的演算法上去。

Abstract
IEEE 802.16 (wireless metro network, WirelessMAN or WIMAX called also) was designed for a metro network which can provide wide band access between several miles in the surface. The performance in data transmitting rate is almost the same as that cable, DSL, or T1 can provide, even can match that IEEE 802.11, wireless LAN system can provide. After the standard IEEE 802.16-2004 was released, the popular modulation technique named OFDM decrease the ISI substantially. According to this standard, I will introduce the transmitter design which fit to standard, inclusive of convolutional code encoder which can provide quite high coding gain, interleaver which can decrease the probability that the burst error may occur, and how to insert pilot tone into data subcarriers just like standard said, the baseband signal processing consists of Inverse Fast Fourier Transform and CP (cyclic prefix) insertion. Since the critical module among the transmitter system will be Inverse Fourier Transform, since IFFT acts just the same as FFT. I will introduce a novel coefficient ordering technique used pipelined FFT which can reduce the switching activity to achieve low power consumption, compare to former parallel FFT processor, the pipelined FFT provide real time property and data ordering technique can be implemented in this long point FFT. Since the only noise source in the transmitter is quantized noise, I will introduce the effect of finite wordlength and the comparison of SNqR in different length of word length also.
Finally, after finishing the hardware description language (verilog) design, I will realize my design on the FPGA platform by using Quartus II tool, thus we can verify the full design in this platform. And others can modify or add new algorithm under this platform in the future.

中文目錄
中文摘要…………………………………………Ⅰ
致謝………………………………………………Ⅱ
英文論文本目錄…………………………………Ⅲ
附錄 英文論文本………………………………..Ⅵ


Contents

Abstract
Contents
Chapter 1 Introduction………………………………………….1
1.1 Introduction of IEEE802.16-2004…………………………………1
1.1.1 Introduction of Wimax……………………………………………………..1
 1.1.2 The Evolution of IEEE 802.16……………………………………………..2
1.1.3 Frequencies Below 11 GHz………………………………………………...4
1.1.4 Air Interface Nomenclature and PHY Compliance………………………...4
1.2 Introduction of OFDM…………………………………………….5
1.2.1 Data Transmission over Multipath Channel………………………………..5
1.2.2 Single Carrier Approach……………………………………………….…...6
1.2.3 Multi Carrier Approach……………………..……………………………...8
1.2.4 Orthogonal Frequency Division Multiplexing……………………………..8
Chapter 2 WirelessMAN-OFDM PHY………………………..11
2.1 OFDM Symbol Description………………………...…………….11
2.1.1 Time Domain…...…………………………………………………………11
2.1.2 Frequency Domain……………………………………...………………...11
2.1.3 Primitive Parameter Definitions……………………………..…………...12
2.1.4 Derived Parameter Definitions…………………………………..……….12
2.1.5 Transmitted Signal………………………………………………………...13
2.1.6 Parameters of Transmitted Signal…..…………………………………….13
2.2 Hardware Implementation ……………………………………….14
2.2.1 System Block Diagram …………………………………………………...14
2.2.2 Randomization……………………………………………………………15
2.2.3 Preamble Structure………………………………………………………..17
2.2.4 Convolutional Encoder……………………………………………………19
2.2.5 Interleaver…………………………………………………………………19
2.2.6 Modulation………………………………………………………………..22
Chapter 3 Foundation of Fast Fourier Transform ……………25
3.1 Introduction………………………………………………………25
3.2 Radix-2 FFT Algorithm…………………………………………..26
3.3 Radix-4 FFT Algorithm…………………………………………..34
3.4 Split-Radix FFT Algorithm………………………………………39
3.5 Comparison and Summary ……………………...……………….42
Chapter 4 The Hardware Implementation of FFT…………….44
4.1 Pipelined FFT…………………………………………………….44
4.1.1 Introduction……………………………………………………………….44
4.1.2 Algorithm Represents………………………………...…………………...44
4.1.3 Commutator……………………………………………………………….46
4.1.4 Butterfly Element…………………………………...…………………….48
4.1.5 Twiddle Factor Generator………………..………………………………..50
4.1.6 Complex Multiplier……………………………………………………….53
4.1.7 Data Ordering………………..…………………………………………...55
4.1.8 The Hardware Sharing of CP Insertion and Data Ordering………..……...57
4.2 Low Power Design for Pipelined FFT……………………...…….58
4.2.1 Introduction……………………………………………………………….58
4.2.2 Algorithm Review………………………..……………………………….60
4.2.3 Ordered Pipelined FFT Architecture…………………...…………………62
4.2.4 Minimum Switching Activity…………………………..………………...63
4.2.5 Commutator Sesign for 256-point Pipelined FFT………………………...67
4.3 Bit Arrangement and the Effect of Finite Word Length...………..70
4.3.1 Bit Arrangement……………...…………………………………………...70
4.3.2 The Effect of Finite Word Length………………………………………...72
Chapter 5 Implementation Result……………..……………...74
5.1 Implementation Environment……………………………………74
5.1.1 Introduction……………………………………………………………….74
5.1.2 Hardware Environment……………..……………………………………75
5.1.3 Software Environment…………………………………………………….76
5.2 Behavior Result……..……………………………………………76
5.2.1 The Behavior Result of Each Module…….………………………………76
5.2.2 The Result and Compare of the SNqR at FFT Output……….…………...82
5.3 The Result and Compare of the FPGA Simulation………..……...85
Chapter 6 Conclusion and Future Work……………...………..91
6.1 Conclusion………………………………………………………..91
6.2 Future Work………………………………………………………91
Bibliography…………………………………………………..92



List of table


Table 1.1: Air interface nomenclature………………………………………………..5
Table 2.1: OFDM symbol parameters………………………………………………13
Table 2.2: Block size of all subchannels…………………………………………….21
Table 3.1: Number of Nontrivial Real Multiplications and Additions to Compute an N-point Complex DFT……………………………………………………………….43
Table 4.1: The transition matrix of switching activity……………………………….64
Table 4.2: Ordered and conventional coefficient sequence for a 16-point radix-4 FFT…………………………………………………………………………………...65














List of figure

Figure 1.1: The range that different standard can cover ……………………………...2
Figure 1.2: The evolution of IEEE 802.16……………………………………………3
Figure 1.3: The difference between IEEE 802.16-2004 and IEEE 802.16e…………..4
Figure 1.4: Multipath transmission in a broadcasting application……………………6
Figure 1.5: Basic structure of a single carrier system………………………………...6
Figure1.6: Effective length of CIR……………………………………………………7
Figure 1.7: Basic structure of a multicarrier system………………………………….8
Figure 1.8: OFDM and the orthogonality principle…………………………………..9
Figure 2.1: OFDM symbol time structure…………………………………………...11
Figure 2.2: OFDM subcarrier description…………………………………………...12
Figure 2.3: Typical block diagram of WirelessMAN transmitter……………………15
Figure 2.4: My block diagram of WirelessMAN transmitter system………………..15
Figure 2.5: PRBS for randomization………………………………………………...16
Figure 2.6: OFDM randomizer downlink initialization vector for burst #2…N…….16
Figure 2.7: OFDM randomizer uplink initialization vector…………………………17
Figure 2-8: Downlink and network entry preamble structure……………………….17
Figure 2.9:   convoloutional code encoder……………………………………….19
Figure 2.10: Block diagram of Interleaver…………………………………………..21
Figure 2.11: BPSK, QPSK and 16 QAM constellations ……………………………22
Figure 2.12: PRBS for pilot modulation…………………………………………….23
Figure 3.1: First step in the decimation-in-time algorithm………………………….28
Figure 3.2: Three stages in the computation of an N = 8-point DFT………………..29
Figure 3.3: Eight-point decimation-in-time FFT algorithm…………………………30
Figure 3.4: Basic butterfly computation in the decimation-in-time FFT algorithm…30
Figure 3.5: Shuffling of the data and bit reversal……………………………………31
Figure 3.6: First stage of the decimation-in-frequency FFT algorithm……………...33
Figure 3.7: Basic butterfly computation in the decimation-in-frequency…………...33
Figure 3.8: N = 8-piont decimation-in-frequency FFT algorithm…………………...34
Figure 3.9: Basic butterfly computation in a radix-4 FFT algorithm………………..36
Figure 3.10 Sixteen-point radix-4 decimation-in-time algorithm with input in normal order and output in digit-reversed order……………………………………………...37
Figure 3.11 Sixteen-point, radix-4 decimation-in-frequency algorithm with input in normal order and output in digit-reversed order……………………………………..38
Figure 3.12: Length 32 split-radix FFT algorithms from paper by Duhamel (1986); reprinted with permission from the IEEE…………………………………………….41
Figure 3.13: Butterfly for SRFFT algorithm………………………………………...42
Figure 4.1: 256 point radix-4 pipelined FFT processor……………………………...46
Figure 4.2: The block diagram of commutator (shift-register form)………………...47
Figure 4.3: Timing and operation of the typical commutator at stage for radix-4 FFT…………………………………………...............................................................48
Figure 4.4: Butterfly element and pipeline used for stage t…………………………49
Figure 4.5: The twiddle factor allocation on the unit circle…………………………51
Figure 4.6: The block diagram of twiddle factor generator…………………………52
Figure 4.7: The block diagram of complex multiplier………………………………54
Figure 4.8: The complex multiplier with a multiplexer …………………………….54
Figure 4.9: The tree diagram for 16-point radix-4 FFT algorithm…………………..56
Figure 4.10: The output order of each stage…………………………………………56
Figure 4.11: OFDM symbol time structure………………………………………….57
Figure 4.12: The block diagram of cp insertion……………………………………..57
Figure 4.13: The signal flow graph of normal 16-point radix-4 FFT    ……………..62
Figure 4.14: The block diagram of N-point pipelined radix-4 FFT…………………62
Figure 4.15: The ordered signal flow graph of 16-point radix-4 FFT algorithm……66
Figure 4.16: Ordered 16-point radix-4 FFT processor architecture…………………67
Figure 4.17: The timing diagram of the order commutator………………………….67
Figure 4.18: Two different form of commutator (a) SR form (b) DM form………...68
Figure 4.19: The timing diagram of 4-commutator (ADM consists)………………..70
Figure 4.20: The bit arrangement of each stage’s output …………………………...71
Figure 4.21: The block diagram of SNqR calculator………………………………..73
Figure 5.1: The cell based design flow……………………………………………...75
Figure 5.2: Picture of Stratix II ……………………………………………………..76
Figure 5.3: The simulation result of input generator and convolutional encoder…...78
Figure 5.4: The operation of Interleaver module……………………………………80
Figure 5.5: The output of data modulation (64-QAM)……………………………...80
Figure 5.6: The simulation result of PBPR and pilot modulation…………………...81
Figure 5.7: The operation in the pilot insertion……………………………………...82
Figure 5.8: The operation of stage 3 of 256-FFT (ordered commutator)……………83
Figure 5.9: The SNqR versus Coefficient word length in different input quantize word length (64-QAM & multiply  at output)………………………………….84
Figure 5.10: The SNqR versus Coefficient word length in different input quantize word length (64-QAM & multiply  at input)…………………………………...85
Figure 5.11: The SNqR versus Coefficient word length in different input quantize word length (according to reference [15])……………………………………………86
Figure 5.12: The behavior simulation at the end of design (Debussy)……………...88
Figure 5.13: The FPGA simulation at the end of design (SignalTap II)…………….89
Figure 5.14: The behavior simulation at the end of design (Debussy)……………...90
Figure 5.15: The FPGA simulation at the end of design (SignalTap II)…………….90

                                

Bibliography

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