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研究生： 杜立偉
Du, Wei-Li
論文名稱： 應用電漿佈植氮化及矽覆蓋層以提升具有矽化鍺或鍺通道之金氧半元件電特性研究
Application of plasma implantaion nitridation and Si cap layer to enhance electrical characteristic for MOS devices with SiGe or Ge channel
指導教授： 張廖貴術
Chang-Liao, Kuei-Shu
口試委員:
學位類別： 碩士
Master
系所名稱： 原子科學院 - 工程與系統科學系
Department of Engineering and System Science
論文出版年： 2009
畢業學年度： 98
語文別： 中文
論文頁數： 113
中文關鍵詞： 矽化鍺或鍺通道 、電漿佈植氮化
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    • 摘要
    為了持續改善元件的性能，金氧半元件之閘極氧化層(SiO2) 的厚度必須繼續縮小，然而極薄的閘極氧化層常伴隨著高的閘極漏電流，為了減少閘極漏電流，high-k 材料已被廣泛使用來取代二氧化矽作為金氧半元件的閘極介電層。然而，high-k 材料仍面臨一些技術性的挑戰例如像charge traping 和遷移率惡化…等問題。
    所以為了克服這些因素才有了介面處理，以及通道利用可以提供較高遷移率的含鍺半導體材料，因為純鍺本身對矽而言，載子遷移率電子提升兩倍至於電洞可以提升四倍，對於元件傳輸可以大大得到改善。但是由於鍺的不耐高溫在400℃下產生易揮發的氣體且容易水解，對於元件的電特性會degradation，所以勢必要用其它鈍化方式來抑制鍺擴散並且維持含鍺通道元件的電特性。
    為了提升含鍺通道元件特性，本論文首先針對矽鍺虛擬基板方面，以鍺濃度30%為基準，做不同堆疊的變換以期許找到抑制鍺擴散最佳結構，以矽鍺通道而言發現以tri-layer 的形式其漏電流較低graded 的形式其可靠度較佳；至於對純鍺通道而言，在不同矽鍺比例下的緩衝層做探討，但由於矽覆蓋厚度3nm 和介電層厚度2nm 太薄，在後續高溫退火PMA 800℃下無法有效阻擋鍺擴散，所以元件漏電流異常大而且發現隨著鍺的比例上升其情況較嚴重。
    為了改善上述純鍺虛擬基板所遇到的問題，接著針對純鍺虛擬基板通道，在介電層厚度4nm 且PMA 700℃下，研究在不同矽覆蓋厚度下做的探討，發現到隨著矽覆蓋厚度上升，元件的基本電性和可靠度SILC 和Stress CV 都得到明顯改善，結果顯示在3nm 矽覆蓋厚度下特性較差而7nm 下為最佳。
    最後為了進一部得到提升元件電特性，針對ALD 成長之HfAlO 為介電層，以電漿浸潤式離子佈植(PIII)的方式，從閘極上方摻雜N 至介電層中。從物性分析SIMS 觀察從閘極上方佈植氮離子是可行的，而且結果顯示，針對矽鍺虛擬基板而言在2.5KeV、10 分鐘下元件可靠度得到提升，至於在純鍺虛擬基板方面以3KeV、10 分鐘下元件EOT 可以達到微縮且可靠度也一樣得到改善。

    目錄 摘要........................................................................................................................ i 致謝......................................................................................................................iii 目錄....................................................................................................................... v 表目錄.................................................................................................................. ix 圖目錄................................................................................................................... x 第一章緒論......................................................................................................... 1 1.1 前言................................................................................................................. 1 1.2 使用High-K 介電材料的原因....................................................................... 1 1.3 高介電材料的選擇......................................................................................... 2 1.4 矽鍺虛擬基板-應變通道................................................................................ 3 1.5 應變對載子遷移率的影響............................................................................. 4 1.6 臨界厚度......................................................................................................... 5 1.7 差排................................................................................................................. 5 1.8 鍺氧化物的特性............................................................................................. 6 1.9 界面缺陷鈍化(Interface defect passivation)................................................... 7 1.10 論文架構....................................................................................................... 8 第二章元件製程與量測................................................................................... 19 2.1 HfAlO 閘介電層在不同矽鍺虛擬基板和純鍺通道下不同矽鍺比例緩衝層 之金氧半元件製作流程..................................................................................... 19 2.1.1 晶片刻號和晶背處理........................................................................ 19 vi 2.1.2 磊晶不同含鍺虛擬基板和閘極介電層沉積.................................... 20 2.1.3 金屬閘極TaN 沉積及退火處理....................................................... 20 2.2 不同矽覆蓋厚度下純鍺虛擬基板搭配介電層材料HfAlO 之金氧半電容 元件製作流程..................................................................................................... 20 2.2.1 晶片刻號和晶背處理........................................................................ 21 2.2.2 磊晶Si/Ge 虛擬基板和閘極介電層沉積......................................... 21 2.2.3 金屬閘極TaN 沉積及佈植離子氮化處理....................................... 21 2.3 金屬閘極TaN (PIII 氮化)搭配ALD 成長之介電層HfAlO/HfO2 在含鍺通 道之金氧半元件製作流程................................................................................. 22 2.3.1 晶片刻號和晶背處理........................................................................ 22 2.3.2 磊晶Si/Si1-xGex 虛擬基板和閘極介電層沉積.............................. 22 2.3.3 金屬閘極TaN 沉積及佈植離子氮化處理....................................... 23 2.4 金氧半電容電性量測................................................................................... 23 2.4.1 電容-電壓 (C-V) 特性量測............................................................ 23 2.4.2 電流-電壓 (I-V) 特性量測.............................................................. 24 2.4.3 遲滯 (Hysteresis) 特性量測............................................................ 24 2.4.4 Stress-Induced Vfb shift (△Vfb) 特性量測........................................ 24 2.5 金氧半電容物性與材料分析...................................................................... 25 2.5.1 二次離子質譜儀(Secondary Ion Mass Spectrometer, SIMS) ........... 25 第三章 HfAlO 閘介電層與各種矽鍺虛擬基板堆疊結構對金氧半元件電特性 之研究................................................................................................................. 28 vii 3.1 研究動機....................................................................................................... 28 3.2 製程與量測................................................................................................... 30 3.2.1 製程條件............................................................................................ 30 3.2.2 測量參數............................................................................................ 31 3.3 實驗結果與討論........................................................................................... 32 3.3.1 介電層HfAlO 在各種不同矽鍺堆疊結構虛擬基板....................... 32 3.3.2 具有純鍺虛擬基板與不同矽鍺比例之緩衝層比較........................ 36 3.4 結論............................................................................................................... 37 第四章探討不同矽覆蓋厚度對純鍺通道元件的影響................................... 50 4.1 研究動機....................................................................................................... 50 4.2 製程與量測................................................................................................... 52 4.2.1 製程條件............................................................................................ 52 4.2.2 測量參數............................................................................................ 53 4.3 實驗結果與討論........................................................................................... 54 4.3.1 MOS 元件具有純鍺虛擬基板及不同矽覆蓋厚度下之電特性比較 ..................................................................................................................... 54 4.3.2 MOS 元件具有純鍺虛擬基板及不同矽覆蓋厚度下之可靠性比較 ..................................................................................................................... 57 4.4 結論............................................................................................................... 58 第五章應用電漿浸潤式氮離子佈植對含鍺通道整合元件之金氧半電特性研 究......................................................................................................................... 71 viii 5.1 研究動機....................................................................................................... 71 5.2 製程與量測................................................................................................... 74 5.2.1 製程條件............................................................................................ 74 5.2.2 量測參數............................................................................................ 75 5.3 實驗結果與討論........................................................................................... 76 5.3.1 PIII 氮化TaN/HfAlO/HfO2 之物性分析........................................... 76 5.3.2 MOS 元件具不同矽鍺比例下通道及PIII 氮化之電特性與可靠度 ..................................................................................................................... 78 5.3.3 PIII 氮化MOS 元件在不同矽覆蓋厚度下純鍺通道...................... 81 5.4 結論............................................................................................................... 84 第六章結論及展望......................................................................................... 104 6.1 結論............................................................................................................. 104 6.2 展望............................................................................................................. 105 參考文獻........................................................................................................... 107 ix 表目錄 表4-1 不同矽覆蓋厚度純鍺虛擬基板之結構圖..................................... 59 表5-1 不同PIII 離子佈植能量、時間以及退火溫度、時間之實驗參數 ............................................................................................................. 85 表5-2 不同矽鍺比例通道下有PIII 氮化與無氮化之實驗參數............. 85 表5-3 不同矽覆蓋厚度下純鍺基板有PIII 氮化與無氮化之實驗參數. 86 x 圖目錄 圖1-1 介電層微縮下產生的問題............................................................. 10 圖1-2 各種介電材料其物理特性比較..................................................... 10 圖1-3 三相圖(a)Ti-O-Si (b)Zr-O-Si 化合物............................................ 11 圖1-4 metal/high-k 所產生的Fermi-level pinning.................................... 11 圖1-5 使用high-k 材料造成散射最重要的議題-Remote phonon scattering ............................................................................................ 12 圖1-6 鍺和矽元素的一些基本特性......................................................... 12 圖1-7 由於矽和鍺的晶格不匹配造成(a)壓縮應變 (b)拉伸應變........... 13 圖1-8 導帶sixfold degenerate 受雙軸拉伸應變前與應變後之圖......... 13 圖1-9 矽導帶受應變後其能帶分佈......................................................... 14 圖1-10 輕電洞和重電洞受雙軸拉升應變後的示意圖........................... 14 圖1-11 (a)矽磊晶在矽鍺上，矽之臨界厚度與鍺含量之曲線圖............ 15 (b)矽鍺磊晶在矽上，矽鍺之臨界厚度與鍺含量之曲線圖 [12]............ 15 圖1-12 矽鍺磊晶在矽基板上，所產生之差排包含(a)錯位差排(misfit dislocation) (b)威脅差排(threading dislocation) ................................ 16 圖1-13 各種鍺氧化物的基本物理性質................................................... 17 圖1-14 介電材料與含鍺界面的整合方法............................................... 17 圖1-15 (a)、(b) ZrO2/Ge 和 (c)、(d) HfO2 /Ge 高溫後混合後情形...... 18 圖2-1 二次質譜儀基本構造..................................................................... 27 圖3-1 不同矽鍺虛擬基板之結構圖......................................................... 38 xi 圖3-2 不同矽鍺比例緩衝層之結構圖..................................................... 38 圖3-3 在矽基板上長一層隨厚度變大而濃度呈現性成長的graded SiGe ............................................................................................................. 39 圖3-4 TEM 觀測圖，差排(黑色線條)被侷限在graded SiGe ............... 39 圖3-5 一般傳統的dual channel 結構，經由改善而變成tri-layer 結構； ε=應變................................................................................................. 40 圖3-6 經由改善而變成tri-layer 結構使載子遷移率得到提升............... 40 圖3-7 在graded layer 沒插應變矽與有插之表面粗糙度比較............... 41 圖3-8 TaN/HfAlO/Chemical ox./Si/SiGe stack/Si 金氧半元件實驗流程圖 ................................................................................... 42_Toc241402464 圖3-9 具有不同矽鍺虛擬基板(a) uniform (b) tri-layer (c) graded (d) uniform+graded 之MOS 電容電壓量測和模擬CV 曲線圖........... 44 圖3-10 具不同矽鍺虛擬基板之MOS 元件漏電流累積圖.................... 45 圖3-11 具不同矽鍺虛擬基板之MOS 元件EOT 和漏電流密度圖....... 45 圖3-12 具不同矽鍺虛擬基板之MOS 元件電容遲滯圖........................ 46 圖3-13 具不同矽鍺虛擬基板之MOS 電容經E=-14MV/cm 在不同stress 時間下的平帶電壓平移量................................................................. 46 圖3-14 具不同矽鍺虛擬基板之MOS 電容經E=-14MV/cm 在不同stress 時間下的漏電流增加量..................................................................... 47 圖3-15 不同矽鍺比例緩衝層(a)SiGe_10 (b)SiGe_20 (c)SiGe_30 之MOS 元件電容電壓量測............................................................................. 48 xii 圖3-16 具有不同矽鍺比例緩衝層(a)SiGe_10 (b)SiGe_20 (c)SiGe_30 之 MOS 元件電流電壓關係圖................................................................ 49 圖4-1 應變矽鍺磊晶在矽基板上的結構能帶圖..................................... 60 圖4-2 應變矽磊晶在矽鍺上的結構能帶圖............................................. 60 圖4-3 由於valence band offset 造成的quantum well 使電洞被侷限示意 圖......................................................................................................... 61 圖4-4 以PVD 成長HfO2 在Ge 上的SIMS 縱深分佈圖。實心圓圈代表 有透過後續高溫退火PDA700℃、空心圓圈代表沒有PDA鍺在HfO2 內的縱深分佈..................................................................................... 61 圖4-5 不同矽覆蓋厚度純鍺虛擬基板之電容結構圖............................. 62 圖4-6 不同矽覆蓋厚度純鍺虛擬基板之金氧半元件實驗流程圖......... 63 圖4-7 具有不同矽覆蓋厚度(a) Ge_3 (b) Ge_5 (c) Ge_7 及純鍺虛擬基板 之MOS 電容量測和模擬的C-V 曲線圖.......................................... 65 圖4-8 具有不同矽覆蓋厚度(a) Ge_3 (b) Ge_5 (c) Ge_7 及純鍺虛擬基板 之MOS 電容在不同頻率量測下的C-V 曲線圖.............................. 66 圖4-9 具不同矽覆蓋厚度Ge_3、Ge_5 和Ge_7 及純鍺虛擬基板之MOS 元件在反轉處之漏電流密度圖......................................................... 67 圖4-10 具不同矽覆蓋厚度Ge_3、Ge_5 和Ge_7 及純鍺虛擬基板之MOS 元件平帶電壓..................................................................................... 67 圖4-11 具不同矽覆蓋厚度Ge_3、Ge_5 和Ge_7 及純鍺虛擬基板之MOS 元件的漏電流累積圖......................................................................... 68 xiii 圖4-12 具不同矽覆蓋厚度Ge_3、Ge_5 和Ge_7 及純鍺虛擬基板的MOS 元件之EOT 和漏電流密度圖........................................................... 68 圖4-13 具不同矽覆蓋厚度Ge_3、Ge_5 和Ge_7 及純鍺虛擬基板之MOS 元件遲滯............................................................................................. 69 圖4-14 具不同矽覆蓋厚度Ge_3、Ge_5 和Ge_7 及純鍺虛擬基板之MOS 元件經不同stress 時間下的平帶電壓平移量.................................. 69 圖4-15 具不同矽覆蓋厚度Ge_3、Ge_5 和Ge_7 及純鍺虛擬基板之MOS 元件經不同stress 時間下的漏電流增加量...................................... 70 圖5-1 電漿浸潤式離子佈植機示意圖..................................................... 87 圖5-2 傳統離子佈值電壓圖5-3 PIII 脈衝電壓.................... 87 圖5-4 不同PIII 離子佈植能量、時間以及退火溫度、時間之示意圖. 88 圖5-5 不同矽鍺比例通道下有PIII 氮化與無氮化之示意圖................. 88 圖5-6 不同矽覆蓋厚度下純鍺基板有PIII 氮化與無氮化之示意圖..... 89 圖5-7 有無PIII 氮化含鍺虛擬基板實驗流程圖..................................... 90 圖5-8 PIII 氮化閘介電層在佈質能量2.5-5 KeV 和時間10min.下之漏電 流密度累積圖..................................................................................... 92 圖5-9 PIII 氮化閘介電層在佈質能量2.5-5 KeV 和時間10min.下之遲滯 圖......................................................................................................... 92 圖5-10 PIII 氮化閘介電層在能量2.5-5 KeV 下之Hf-N 鍵結縱深分佈圖 ............................................................................................................. 93 圖5-11 退火溫度700-900℃下之Hf-N 鍵結縱深分佈圖...................... 93 xiv 圖5-12 退火秒數30-60 秒下之Hf-N 鍵結縱深分佈圖......................... 94 圖5-13 具鍺含量為(a) 10% (b) 20% 之SiGe 虛擬基板及沒有PIII 氮化 之MOS 電容量測和模擬的C-V 曲線圖.......................................... 95 圖5-14 具鍺含量為 (a) 10% (b) 20% (c) 30% 之SiGe 虛擬基板經PIII 氮化之MOS 電容量測和模擬的C-V 曲線圖.................................. 96 圖5-15 MOS 元件具不同鍺含量之矽鍺虛擬基板與有無PIII 氮化之EOT 比較..................................................................................................... 97 圖5-16 MOS 元件具不同鍺含量之矽鍺虛擬基板與有無PIII 氮化比較之 EOT 和漏電流密度圖........................................................................ 97 圖5-17 MOS 元件具不同鍺含量之矽鍺虛擬基板與有無PIII 氮化之遲滯 比較..................................................................................................... 98 圖5-18 MOS 元件具不同鍺含量之矽鍺虛擬基板與有無PIII 氮化經不同 stress 時間下的平帶電壓平移量....................................................... 98 圖5-19 MOS 元件具不同鍺含量之矽鍺虛擬基板與有無PIII 氮化經不同 stress 時間下的漏電流增加量........................................................... 99 圖5-20 具矽覆蓋厚度為 (a) 3nm (b) 5nm (c) 7nm 之純鍺虛擬基板及有 PIII 氮化之MOS 電容量測和模擬的C-V 曲線圖........................ 100 圖5-21 具不同矽覆蓋厚度純鍺虛擬基板下及有無PIII 氮化之MOS 元 件漏電流累積圖............................................................................... 101 圖5-22 具不同矽覆蓋厚度純鍺虛擬基板及有無PIII 氮化之MOS 元件 EOT 和漏電流密度圖...................................................................... 101 xv 圖5-23 具不同矽覆蓋厚度純鍺虛擬基板及有無PIII 氮化之遲滯比較 ........................................................................................................... 102 圖5-24 具不同矽覆蓋厚度純鍺虛擬基板及有無PIII 氮化之MOS 電容經 E=-12MV/cm 在不同stress 時間下的平帶電壓平移量................. 102 圖5-25 具不同矽覆蓋厚度純鍺虛擬基板即有無PIII 氮化之MOS 電容經 E=-12MV/cm 在不同stress 時間下的漏電流增加量..................... 103

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