用於非同步系統之多用途封裝電路｜國立清華大學博碩士論文庫

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研究生：	鄧揚駿 Deng, Yang-Jiun
論文名稱：	用於非同步系統之多用途封裝電路 A General Purpose Wrapper for Asynchronous Systems
指導教授：	張彌彰 Chang, Mi-Chang
口試委員:	馬席彬 Ma, Hsi-Pin 郭治群 Guo, Jyh-Chyurn
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2011
畢業學年度：	100
語文別：	英文
論文頁數：	85
中文關鍵詞：	非同步、封裝電路、平均情況表現、可停止之時脈產生器、完成電路
外文關鍵詞：	Asynchronous, Wrapper, Average case performance, Pausible clock controller, Done circuit
相關次數：	點閱：3 下載：0
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整體非同步局部同步（GALS）設計對於實現非同步系統是個有效率的方式。但是一般非同步封裝電路所包的局部同步區塊工作在最壞情況的表現。為了達到平均情況的特性以及容易實現非同步系統，本論文提出一個多用途封裝電路內含控制電路與”可停止之時脈產生器（PCC）”以及”完成電路”合作。這些電路所組成的非同步封裝電路可用於同步電路和組合電路。此控制電路內含寫埠、讀埠和完成訊號處理電路。我們用兩種不同的方法設計：一種全為標準元件組成，使用者可用此版本在前段數位流程實現並驗證非同步系統；另一種則是用C元件（C-elements）實現，為了使非同步系統能有更好的效能如小面積和低耗能。再者，為了使得非同步系統中的資料正確地傳輸，三種非同步封裝電路的連接方式被介紹，分別為一對一、一對多及多對一。使用者能夠使用提出的非同步封裝電路建構出非同步系統，例如整體非同步局部同步（GALS）系統或是非同步管線（Pipeline）。最後我們分析此非同步封裝電路在兩級之間傳輸資料時所消耗的時間，並給使用者建議以能適當的使用此封裝電路。

Globally asynchronous locally synchronous (GALS) design is an efficient way to implement asynchronous systems. However, the locally synchronous (LS) modules with asynchronous wrappers make worst case performance. In order to achieve average case performance and facilitate asynchronous circuits design, this thesis proposes a general purpose wrapper that includes control circuits to cooperate with pausible clock controllers (PCC) and done circuits. The asynchronous wrappers using these circuits can wrap around not only synchronous blocks (with clock) but also combinational modules. The control circuits contain the write-port, read-port, and done-handling circuit. There are two implementations: one using standard cell library and the other using c-elements. The system using the former design can be implemented and verified conveniently using existing frond-end synchronous design flow. The latter is implemented for better performance, higher speed, smaller area and lower power consumption. Moreover, the proper ways of using the asynchronous wrappers for robust data communication in asynchronous systems are introduced. There are one-to-one, one-to-many and many-to-one communications. Users can use the wrappers to construct asynchronous systems such as GALS systems and asynchronous pipelines. Finally, the timing overhead of the asynchronous wrappers between local modules is analyzed. Guidelines for proper usage are also given.

摘要    i
Abstract    ii
誌謝    iii
Contents    iv
List of Figures    vii
List of Tables    x
Chapter 1 Introductions    1
1 Background    1
2 Motivation    2
3 Organization    3
Chapter 2 Basics of Asynchronous Design    4
1 Properties of Asynchronous Design    5
2 Typical Asynchronous Designs    6
3 Popular Handshake Protocols    8
3.1 Bundled-data    8
3.2 Dual-rail    10
4 C-elements    12
4.1 Implementations of C-elements    12
4.2 The C-element with Standard cells    16
5 Asynchronous Pipelines and Done circuits    19
6 Starvation and Blocking    21
7 Overview of GALS Design    21
8 Related Works of an Asynchronous Wrapper    24
Chapter 3 Proposed Asynchronous Wrappers    28
1 Structures of the Asynchronous Wrappers    29
1.1 The Asynchronous Wrapper for Combinational Module    29
1.2 The Asynchronous Wrapper for Synchronous Module    32
1.3 Latches or Flip-Flops for Registers    34
2 Implementation with Standard cells    35
2.1 Write-port and Read-port with Standard cells    35
2.2 Done-Handling Circuit with Standard cells    39
2.3 Pausible Clock Controller (PCC) with Standard cells    41
3 Implementation with C-elements    43
3.1 Write-port and Read port with C-elements    43
3.2 Done-Handling Circuit with C-elements    45
3.3 Pausible Clock Controller (PCC) with C-elements    46
4 Simulation Results of the Asynchronous Wrappers    47
5 Timing Constraints for Latches or Flip-Flops    53
Chapter 4 Communications with the Asynchronous Wrappers    57
1 One-to-one Communication    58
1.1 Structure of One-to-one Communication    58
1.2 One-to-one connection of the Asynchronous Wrappers    59
2 One-to-many and Many-to-one Communications    64
2.1 Structures of One-to-many and Many-to-one Communications    64
2.2 One-to-many and Many-to-one connections of the Asynchronous Wrappers    66
3 Timing Overhead of the Asynchronous Wrappers    67
4 Timing Overhead of Data Communication    68
5 Application    71
Chapter 5 Conclusions and Future Works    73
1 Conclusions    73
2 Future Works    74
References    75
Appendix    78

                                

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[8] Z. Al Tarawneh, G. Russell and A. Yakovlev, "An Analysis of SEU Robustness of C-element Structures Implemented in Bulk CMOS and SOI Technologies," 2010 International Conference on Microelectronics, ICM, pp. 280-283, 19-22 Dec. 2010.

[9] R. P. Bastos, G. Sicard, F. Kastensmidt, M. Renaudin and R. Reis, "Evaluating Transient-fault Effects on Traditional C-element's Implementations," 2010 IEEE 16th International On-Line Testing Symposium, IOLTS, pp. 35-40, 5-7 July 2010.

[10] T. Kumaran, M. Santhi, M. Srikanth, N. Srinivasan, M. Balaji and G. Lakshminarayanan, "Transient Current Sensing Based Completion Detection with Event Separation Logic for High Speed Asynchronous Pipelines," 2009 IEEE Region 10 Conference, pp. 1-6, 23-26 Jan. 2009.

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[16] R. Mullins and S. Moore, "Demystifying Data-Driven and Pausible Clocking Schemes," 13th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2007, pp. 175-185, 12-14 March 2007.

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[18] R. Ginosar, "Fourteen Ways to Fool your Synchronizer," Proceedings of the Ninth International Symposium on Asynchronous Circuits and Systems, pp. 89-96, 12-15 May 2003.

[19] J. Muttersbach, T. Villiger and W. Fichtner, "Practical Design of Globally-asynchronous Locally-synchronous Systems," Proceedings of the Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems, ASYNC 2000, pp. 52-59, 2000.

[20] Z. Shengxian, L. Weidong, J. Carlsson, K. Palmkvist and L. Wanhammar, "An Asynchronous Wrapper with Novel Handshake Circuits for GALS Systems," IEEE 2002 International Conference on Communications, Circuits and Systems and West Sino Expositions, vol. 2, pp. 1521-1525, 29 June-1 July 2002.

[21] S. Y. Yeh, "An Asynchronous Circuit Front-end Design Flow with Synchronous CAD Tools," 2011.

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