最近幾年，隨著行動電子裝置往高效能、易於攜帶發展，電子產品內部中的元件也是以縮小尺寸與高效能為目標。電子封裝技術從較早期的DIP(Dual in-line Packaging)、QFP(Quad Flat Packaging)、QFJ(quad flat J-leaded Packaging)隨著電子產品小型化和高密度化的需求，覆晶(Flip Chip)、晶片尺寸封裝(Chip Scale Packaging)、晶圓級封裝(Wafer level Packaging)、面板級封裝(Panel level Packaging)等封裝技術相繼被發明。
面板級封裝是指先在載板上進行封裝製程，等到封裝製程結束後再切割成單顆IC的一種封裝技術。其製程與晶圓級封裝非常類似，區別在於晶圓級封裝是在晶圓上進行封裝，而面板級封裝是在載板上進行封裝。面板級封裝比晶圓級封裝優勢的地方在於，面板與晶片皆為矩形，因此晶片在面板上能夠更緊密的排列，材料的使用上更為節省。
面板級封裝製程中，封膠製程會將電子封裝結構加熱，製程結束後在降回室溫，在這段過程中會有兩個因素導致面板產生翹曲的情形。第一個原因為封膠所使用的環氧樹脂在加熱後會產生固化反應，固化反應會使環氧樹脂產生收縮，因而導致翹曲的現象。第二個原因為電子封裝結構中不同材料之間的熱膨脹係數不匹配，封膠製程結束後降回室溫會導致不同材料有不同的收縮量，因而導致翹曲的現象。過大的翹曲量可能會導致接續的封裝製程無法進行，所以需要去預估和控制。
目前最常使用來預估翹曲量的方法為有限元素法模擬，但是封裝結構中有高分子有機材料環氧樹脂，要準確預估翹曲量，需要有環氧樹脂因固化反應所產生的收縮以及不同溫度下的熱膨脹係數。但是這些材料參數不好取得，因此本文中會使用實際晶圓封膠製程後的翹曲量搭配有限元素法模擬，來取得等效熱膨脹係數。接著利用得到的熱膨脹係數建立面板模型，並進行元素尺寸分析，使面板模型元素數量不會太多又能保持模擬結果的準確性。

　For recent years, as mobile electrical devices are developed to high efficiency and become portable, people shrink components inside the electronic devices and improve efficiency at the same time. Electronic package technique from early DIP(Dual in-line Packaging)、QFP(Quad Flat Packaging)、QFJ(quad flat J-leaded Packaging)、TQFP(Thin Quad Flat Packaging) and BGA(Ball Grid Array) to recent miniaturized and high-intensity electric component such as FC(Flip Chip)、CSP(Chip Scale Packaging)、WLP(Wafer level Packaging)、PLP(Panel level Packaging)、3D packaging(Three Dimension Packaging)、and SIP (System in Packaging), etc. have been invented.
PLP(Panel level Packaging) means a packaging technique that conducting packaging process on glass carrier at first, then dividing into several individual IC(Integrated Circuit) after packaging process. This process is similar with WLP(Wafer level Packaging). The difference between them is that the former executed packaging on glass carrier, the latter executed packaging on wafer. The advantage of PLP(Panel level Packaging) is that its size of carrier and IC is rectangle so IC can be arrayed more close. Moreover, the cost of material would be eliminated. However, WLP(Wafer level Packaging) can’t apply this method, hence it would waste extra cost.
In process of PLP(Panel level Packaging), molding process would heat the electronic package structure, then cooling down to room temperature after the end of the process. In this process would have two factor to make carrier generate warpage. The first reason is that epoxy used for molding would lead curing reaction after heating. Curing reaction would make epoxy shrink then generating warpage. The second reason is that CTE(Coefficient of Thermal Expansion) mismatch between different material lead warpage after the end of process and cooling down to room temperature. Overmuch amount of warpage would lead subsequent packaging process interrupted so we need to estimate and control the amount of warpage.
Current method used to estimate is FEM(Finite Element Method) analysis. However, there is polymer organic epoxy resin in package structure. For the purpose of estimating amount of warpage, we need some information for epoxy such as the amount of shrinkage by curing and CTE(Coefficient of Thermal Expansion) in different temperature. Therefore, this paper would apply the actual amount of warpage after molding process with FEM(Finite Element Method) analysis to acquire equivalent CTE(Coefficient of Thermal Expansion). So as to control element amount and maintain correct simulation result simultaneously, this paper make use of equivalent CTE(Coefficient of Thermal Expansion) to establish panel model and conduct element size effect analysis.

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