非晶矽薄膜電晶體之技術研究｜國立清華大學博碩士論文庫

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研究生：	張大山 Ta-Shan Chang
論文名稱：	非晶矽薄膜電晶體之技術研究 Investigation on Technology of Amorphous Silicon Thin-Film Transistor
指導教授：	葉鳳生 Fon-Shan Yeh 張鼎張 Ting-Chang Chang
口試委員:
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering
論文出版年：	2007
畢業學年度：	95
語文別：	英文
論文頁數：	121
中文關鍵詞：	薄膜電晶體
外文關鍵詞：	TFT
相關次數：	點閱：3 下載：0
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本論文提出一種具有低介電係數材料HSQ當做背通道蝕刻非晶矽薄膜電晶體的保護層。由於低介電常數材料HSQ具有高穿透率以及平坦化能力，故而當作薄膜電晶體之保護層可以提升薄膜電晶體液晶顯示器的亮度及開口率。
此外，和傳統以氮化矽薄膜為保護層之非晶矽薄膜電晶體相比，以HSQ為保護層之非晶矽薄膜電晶體效能更為優良。這是由於HSQ薄膜中所含有之氫鍵可以有效的消除非晶矽薄膜電晶體背通道和保護層介面間的density of states，並增加非晶矽通道中的氫含量。本實驗的結果顯示經由HSQ保護之非晶矽薄膜電晶體field-effect mobility為0.57 cm2/Vs、subthreshold swing為0.68V。
接著，新穎的旋塗感光性低介電係數材料，PS-MSZ，在此被提出來應用在背通道蝕刻非晶矽薄膜電晶體上，以做為保護層。此材料可以藉由i-line直接顯影出圖像來，避免掉原本蝕刻之動作。PS-MSZ同樣具備良好的穿透率及平坦化能力，故而除了可以降低gate line與data line間的RC延遲外，也可以提升薄膜電晶體液晶顯示器面板之開口率。並且，PS-MSZ所具備之直接顯影技術不僅可簡化製程流程，此外不需要再進真空系統以及蝕刻步驟可大幅降低成本需求。其應用於背通道蝕刻非晶矽薄膜電晶體上並不影響其電性，且由於其為旋塗製程，不會傷害到背通道，故而在小的負偏壓操作時具備小的背通道漏電流。除此之外，另一個新穎polymer感光材料，在此也同時提出當做保護層用，以和PS-MSZ作對比。
本論文也研究探討非晶矽薄膜電晶體之背通道效應，對非晶矽薄膜與保護層間之背通道漏電機制提出解釋。主要影響背通道效應的因素為fixed charge以及interface state。此二者對薄膜電晶體在小偏壓操作時有較大之影響。Fixed charge將使能帶彎曲，造成電子積聚於背通道處形成漏電。在此我們在不同溫度下，以正反掃之量測方式確認其機制。當元件由20V ~ -20V量測，元件之起始電壓上升、背通道漏電下降。此乃由於大量電子於起使時即被trap在非晶矽薄膜中阻障了其他電子的進入，包括背通道之處。這些被捕獲於非晶矽薄膜中之電子造成了一位障，特別是在小電壓操作之情況下阻擋了電子導通。這種情況我們稱之為space-charge-limited current conduction (SCLC)。此為一暫態效應。然而在高溫下，這些暫態電子將受激發躍出使得此位障消失，元件的導通型態回到原始情況。此現象證fixed charge以及interface state確實是主要影響背通道漏電之主要原因。
本論文最後研究雙閘極非晶矽薄膜電晶體。由於此種元件多了一導通路徑於背通道處，故而較之傳統電晶體具備更佳導通能力。背閘極施加正偏壓時，將會使汲極電流增加。此外，雙閘極薄膜電晶體還具備了比傳統薄膜電晶體更加優良之抗光電流能力。當背閘極由正轉為負時，導帶與價帶受其影響轉為上彎，使得在照光下激發之電子電洞對受到侷限，因而被非晶矽薄膜中之density of state捕獲而複合，此外，背閘極為負偏壓時，Fermi level會較靠近價帶，此時光激發之電子電洞對在產生後將會面對到更多的tail state，因而立刻被複合。

A low-dielectric-constant (low-k) material, siloxane-based hydrogen silsesquioxane (HSQ), is investigated as a passivation layer in bottom-gate hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs). The low-k HSQ film passivated on TFT promotes the brightness and aperture ratio of TFT-LCD due to its high light transmittance and good planarization. Also, the performance of a-Si:H TFT with HSQ passivation has been improved, compared to a conventional silicon nitride (SiNx) passivated TFT, due to that the hydrogen bonds of HSQ assist the hydrogen incorporation to eliminate the density of states between back channel and passivation layer. Experimental results exhibit an improved field-effect mobility of 0.57 cm2/Vs and subthreshold swing of 0.68 V.
Next, a novel spin-on low-k material, photosensitive Polymethylsilazane (PS-MSZ), directly patterned by i-line stepper has been investigated for BCE a-Si TFT passivation layer. The presence of PS-MSZ with good transmittance and planarization reduces the RC delay between gate and data-line, and promotes the aperture ratio of TFT-LCD panel. The direct patterning technique simplifies the process, decreasing cost without the vacuum system and etching steps. The TFT transfer characteristics are not significantly impacted by the PS-MSZ passivation layer. In addition, the PS-MSZ passivated TFT has low leakage current in reverse subthreshold region due to its spin-on deposition. On the other hand, another new direct pattern low-k material, polymer, will also be proposed to be a passivation layer and to compare with PS-MSZ film, which can also applied on TFT device.
On study the back channel effect, the mechanism of back channel leakage between a-Si:H film and passivation layer has been demonstrated. There are two factors affected back channel leakage very much. These factors are fixed charge and interface states. These factors will impact TFT reverse subthreshold characteristics (operation bias at small negative gate voltage) and lead to back channel effect. Fixed charges bend the band and accumulate electrons at back channel. We use forward and reverse sweep measurement at different temperature to confirm back channel leakage mechanism. When TFT device is operated at Vg= 20 ~ -20V, there is a different phenomenon which let threshold voltage increased and back channel leakage decreased. There are lots of electrons trapping in amorphous silicon film when the initial operating voltage is a large positive bias. These trapping electrons will block other electrons entering amorphous silicon film, including back channel region. These trapping electrons in amorphous silicon film made an additional barrier which blocked electron transition, especially at small gate bias operation. This kind of conduction mechanism is similar to space-charge-limited current conduction (SCLC). These trapping electrons in amorphous silicon film are temporary. Therefore, these trapping electrons will be excited at a high temperature environment. Once trapping electrons excited, the blocking barrier decreases and the device conduction mechanism is back to initial type. Therefore, for TFT transfer characteristics, fixed charges existing passivation layer and interface states is the main reason which result in back channel leakage.
The dual-gate a-Si:H TFT owns superior conducting ability than conventional TFT which contains an additional electron path at back channel. Positive back gate bias leads to an increasing in drain current. The dual-gate a-Si:H TFT also exhibits the better endurance against photo leakage current than conventional a-Si:H TFT. When dual gate driving bias becomes negative, conduction band and valence band are bending up by dual gate which lead the photo excited electron-hole pairs to be confined. The confined electron-hole pairs may be easily recombined by lots of DOS in a-Si:H film. Otherwise, under negative dual gate bias, Fermi level is near valence band. At this time, photo excited electron-hole pairs would probably be recombined immediately by those lots of traps when they generated.

Contents
Chinese Abstract　    ------------------------------------------------------------- i
English Abstract　    ------------------------------------------------------------- iii
Acknowledgement ------------------------------------------------------------- vi
Contents　    ---------- ----------------------------------------------------------- viii
Figure Captions　     ------------------------------------------------------------- x
Chapter 1    Introduction
  1.1 General Background　    ---------------------------------------------------    1
  1.2 Organization of the dissertation   ------------------------------------- 9

Chapter 2     Improvement of a-Si:H TFT performance with low-k HSQ passivation layer
  2.1 Introduction　    -------------------------------------------------------------    17
  2.2 Experimental Procedure  -    ---------------------------------------------    19
  2.3 Results and Discussions　    ----------------------------------------------    20
  2.4 Conclusions  -------------------------------------------------------------25

Chapter 3    Novel direct patterned low-k material passivated on BCE a-Si:H TFT for AMLCD
  3.1 Introduction　    -------------------------------------------------------------    39
  3.2 Experimental Procedure  ---------------------------------------------    41
  3.3 Results and Discussions  ---------------------------------------------- 42
  3.4 Conclusions  ------------------------------------------------------------    45

Chapter 4    Back channel leakage analysis of a-Si:H TFT for Temperature effect
  4.1 Introduction　    -------------------------------------------------------------61
  4.2 Experimental Procedure　    ---------------------------------------------    62
  4.3 Results and Discussions　    ----------------------------------------------    63
  4.4 Conclusions   -----------------------------------------------------------    65

Chapter 5    Investigation of a-Si dual-gate TFTs
  5.1 Introduction　     ---------------------------------------------------------- 78
  5.2 Experimental Procedure  --------------------------------------------- 79
  5.3 Results and Discussions　    --------------------------------------------- 81
  5.4 Conclusion    s  ------------------------------------------------------------ 87

Chapter 6    Conclusions and Suggestions for Future Work
  6.1 Conclusions ------------------------------------------------------------- 105
  6.2 Suggestions for Future Work --- ------------------------------------- 108

References　-----------------------------------    --------------------------------------------109
Vita  -----------------------------------------------------------------------------------------119
Publication List  ------------------------------------------------------------------------120

Figure Captions
Chapter 1
Fig. 1-1    a-Si:H TFT application for different panel size.
Fig. 1-2    Basic configuration of a TFT-LCD.
Fig. 1-3   Four structures for a-Si TFTs.
Fig. 1-4    Three possible mechanisms of leakage current in poly-Si TFTs, including thermionic emission, thermionic field emission and pure tunneling.
Fig. 1-5  High aperture ratio BCE a-Si:H TFT with a thick transmittance passivation layer.
Fig. 1-6  The cross-section of interconnect system with parasitic capacitance.

Chapter 2
Fig. 2-1    (a) The cross section of the inverted-staggered a-Si:H TFT with the SiNx passivation.
         (b) The cross section of the inverted-staggered a-Si:H TFT with the HSQ passivation.
Fig. 2-2     FTIR spectra of HSQ before and after a series of curing temperatures.
Fig. 2-3    The optical transmittance of the SiNx and HSQ films with different process temperatures.
Fig. 2-4    The current density-electric field (J-E) curves of HSQ measured by visible light illumination at room temperature.
Fig. 2-5    The Id-Vg transfer characteristics of BCE a-Si:H TFTs with 350℃, 330℃, and 300℃ curing HSQ passivation, respectively.
Fig. 2-6    The Id-Vg transfer characteristics of BCE a-Si:H TFTs at Vd=10V. Solid line, dashed line and broken dashed line represent the TFTs with the HSQ passivation, with the SiNx passivation and standard, respectively.
Fig. 2-7    (a) On current of BCE a-Si:H TFTs with 350℃, 330℃, and 300℃ curing HSQ passivation, respectively.
         (b) On current of BCE a-Si:H TFTs with the HSQ passivation, the SiNx passivation and standard, respectively.
Fig. 2-8    Threshold voltage variation of the HSQ passivated a-Si:H TFT after several times measurement.
Fig. 2-9    Threshold voltage variation of the HSQ passivated a-Si:H TFT after stress.
Fig. 2-10    The ID-VG relationships of the TFTs after bias temperature stress. The threshold voltage shift of structure A and C is 1.75V and 0.75V, respectively.
Tab. 2-1  (a) Stress comparison of HSQ and PE-SiNx films, respectively.
         (b) Adhesion comparison of HSQ and PE-SiNx films, respectively.
Tab. 2-2  The values of the device parameters of the a-Si:H TFTs with HSQ passivation, with the SiNx passivation and standard, respectively.

Chapter 3
Fig. 3-1    Schematic diagram of MSZ (base polymer) and MSQ (cured film).
Fig. 3-2    The cross section of the inverted-staggered a-Si:H TFT with (a) SiNx passivation; (b) low-k passivation.
Fig. 3-3    (a) Fourier-transform infrared spectroscopy (FTIR) spectrum of thermally cured PS-MSZ films.
         (b) Fourier-transform infrared spectroscopy (FTIR) spectrum of thermally cured polymer films.
Fig. 3-4    (a) The scanning electron microscope (SEM) photograph of the via hole of PS-MSZ film with 90oC prebaking patterned on aluminum.
         (b) The scanning electron microscope (SEM) photograph of the via hole of PS-MSZ film with 220oC curing patterned on aluminum.
Fig. 3-5    The scanning electron microscope (SEM) photograph of the good planarization property of PS-MSZ film with 220oC curing.
Fig. 3-6    (a) Adhesion force comparison of different film on silicon substrate.
         (b) Adhesion force comparison of N,Y, and SiNx film on different metal substrate, respectively.
Fig. 3-7    Stress comparison of N,Y, and SiO2, SiNx film on Si substrate, respectively.
Fig. 3-8    The leakage current density-electric field curves (J-E) of as cured N,Y films.
Fig. 3-9    (a) The leakage current density-electric field curves (J-E) of as cured polymer films, and polymer films which were dipped in oxalic acid and DI water for 1 min.
         (b) The leakage current density-electric field curves (J-E) of as cured PS-MSZ films, and PS-MSZ films which were dipped in oxalic acid and DI water for 1 min.
Fig. 3-10    The Id-Vg transfer characteristics of BCE a-Si:H TFTs with N,Y passivation, with the SiNx passivation operated at Vd=10V (W / L =30um / 10um).
Fig. 3-11    The Id-Vg transfer characteristics of BCE a-Si:H TFTs with Y passivation, with the SiNx passivation and standard operated at Vd=10V (W / L =20um / 10um).

Chapter 4
Fig. 4-1    Schematic diagram of a-Si:H TFT with different factors which may affect back channel leakage.
Fig. 4-2    The effect of introducing finite values of vb, and Qb when Nf =1017 and 1016 cm-3 eV-1.
Fig. 4-3    (a) Id-Vg transfer characteristics of conventional BCE a-Si:H TFT at 30oC.
         (b) Id-Vg transfer characteristics of conventional BCE a-Si:H TFT at 60oC.
         (c) Id-Vg transfer characteristics of conventional BCE a-Si:H TFT at 90oC.
         (d) Id-Vg transfer characteristics of conventional BCE a-Si:H TFT at 120oC.
Fig. 4-4    (a) Band diagram of conventional BCE a-Si:H TFT which is operated under negative gate bias.(Vg= -20 ~ 20V)
(b) Band diagram of conventional BCE a-Si:H TFT which is operated under negative gate bias.(Vg= 20 ~ -20V)
Fig. 4-5    (a) Id-Vg transfer characteristics of STD BCE a-Si:H TFT at 30oC.
(b) Id-Vg transfer characteristics of STD BCE a-Si:H TFT at 60oC.
(c) Id-Vg transfer characteristics of STD BCE a-Si:H TFT at 90oC.
(d) Id-Vg transfer characteristics of STD BCE a-Si:H TFT at 120oC.

Chapter 5
Fig. 5-1    The cross section of the inverted staggered BCE dual gate a-Si:H TFT.
Fig. 5-2    The standard Id-Vg characteristics of back Gate TFT structure.
Fig. 5-3    The Id-Vg curve of back gate TFT with Vg range around 0 ~ -5V.
Fig. 5-4    The band diagram of negative Vg operation BG a-Si:H TFT with different BG voltage (Vg < 0V).
Fig. 5-5    The Id-Vg curve of back gate TFT with Vg range around 0 ~ 20V.
Fig. 5-6    The band diagram of positive Vg operation BG a-Si:H TFT with different BG voltage (Vg > 0V).
Fig. 5-7    The Fermi level in BG a-Si:H TFT band gap under positive Vg operation with VBG = 0V and VBG < 0V, respectively.
Fig. 5-8    The cross section of the inverted staggered BCE dual gate a-Si:H TFT with +50V stress for 10000s.
Fig. 5-9    Id-Vg transfer curves of BG a-Si:H TFT (BG common) before and after BG stress with Vd = 0.5V and Vd = 12V, respectively.
Fig. 5-10    Id-Vg transfer curves of BG a-Si:H TFT (BG = 10V) before and after BG stress with Vd = 0.5V and Vd = 12V, respectively.
Fig. 5-11    Photo current generation mechanism process at different negative gate bias operation.
Fig. 5-12    The cross section of the inverted staggered BCE dual gate a-Si:H TFT (bottom gate and back gate are shorted).
Fig. 5-13    Comparison of dual gate a-Si:H TFT Id-Vg transfer curves and BG a-Si:H TFT (Vd = 12V).
Fig. 5-14    Id-Vg transfer characteristics of dual gate a-Si:H TFT and BG a-Si:H TFT at Vd=12V under backlight 3000 nits illumination.
Fig. 5-15 Band diagram of dual gate a-Si:H TFT under backlight illumination.
Fig. 5-16 Band gap of dual gate a-Si:H TFT under backlight illumination.

                                

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[5.14] C. van Berkel and M. J. Powell, Appl. Phys. Lett., 51, pp.1094, 1987.
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