基於記憶體容錯法之共生控制器設計｜國立清華大學博碩士論文庫

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研究生：	郭書輔 Kuo, Su-Fu
論文名稱：	基於記憶體容錯法之共生控制器設計 A Memory-Based Approach for Symbiotic Controller Design
指導教授：	吳誠文 Wu, Cheng-Wen
口試委員:	黃錫瑜 Huang, Shi-Yu 李進福 Li, Jin-Fu 洪浩喬 Hong, Hao-Chiao
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2017
畢業學年度：	106
語文別：	英文
論文頁數：	42
中文關鍵詞：	錯誤更正碼、記憶體、可靠度、在線測試、共生系統
外文關鍵詞：	error correction codes, memory, reliability, on-line testing, symbiotic system
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近幾年物聯網被認定為是半導體產業成長最重要的推手，然而因為全世界的經濟規模以及能源產出並沒有大幅度的成長，所期望的大量的物聯網裝置系統會被成本以及能源消耗所限制。為了解決這類問題，共生系統模型被提出用來設計符合成本效益的裝置系統，以達到低成本、低能源消耗、以及高可靠度的設計。在本篇碩士論文中，我們提出一個基於記憶體容錯法之共生控制器設計。控制器在許多數位系統中是不可或缺的存在而且時常負責很重要的功能，因此我們把目標針對在控制器。在設計數位控制器時邏輯化簡是一個非常有效的方法，它能夠任意操作不影響結果的項使得實現的硬體設計能達到更小的硬體複雜度以及更好的表現。然而，邏輯化簡只保證所設計的狀態不會被更動，當有錯誤發生時，系統將有機會跳到一個未定義的狀態並且造成危險。在正常運作下時，系統應該要一直在我們所設計的狀態下做轉移並且產生我們所設計的控制訊號。為了防止共生控制器進入到未定義的狀態，我們提出一個記憶體模型並且將所提出的方法利用記憶體模型來描述。對於共生控制器設計，我們利用在記憶體中常使用的錯誤更正碼來進行錯誤的更正。除此之外，我們也設計一個不合法狀態的偵測函數來檢測目前的系統狀態是否為合法。實驗結果顯示我們的方法有1.75倍的可靠度的提升，而且如果控制器中越多的控制訊號使用我們的方法，將會有更好的可靠度。當控制器系統失靈時，我們所提出的修復更正的方法也能確保系統輸出安全的控制訊號。

Internet of Things (IOT) has long been identified to be the next driver for the growth of semiconductor industry. However, due to limited world economy scale and power supply, the expected growth of IOT devices and systems will be constrained by their total cost and energy consumption. Symbiotic system (SS) model is proposed to model and design reliable and cost-effective devices and systems, exploring devices and systems with low cost, low energy consumption and high reliability [3]. In our work we propose a memory-based approach to realize symbiotic controller hardware design. We target on controllers since they are the core of the digital systems, and they handle the primary function (work) of a typical device or system. Logic optimization is a very important technique for designing digital controller. It exploits the unknown value (don’t-care value) for optimization, so that the hardware complexity can be lowered and/or the performance can be improved. However, logic optimization only cares about the specified states (legal states). When a fault occurs, the system may reach an undefined state (illegal state) and may cause hazards. In normal operation, the system should always operate in legal states and produce legal outputs. To prevent the symbiotic system from illegal states, we propose a memory-based model and adopt the error correction code approach for symbiotic controller design, reusing a very popular technique for memory reliability improvement. Also, an illegal state detect function is designed in the controller to check if the current state is a legal state. Experimental results show that the system reliability with the proposed approach can be enhanced by 1.75 times and can be further improved if we apply our approach to more signals. Moreover, when the system fails, the remapping mechanism will force the system to output safe control signals.

摘要    i
Abstract    ii
Table of Content    iii
List of Figures    iv
List of Tables    v
Chapter 1 Introduction    1
1.1    Motivation    1
1.2    Related Works    3
1.3    Proposed Approach    3
1.4    Thesis Organization    4
Chapter 2 Background    6
2.1    Error Correction Code    6
Chapter 3 Proposed Approach for Designing Symbiotic Controller    8
3.1    Exhaustive State Diagram    8
3.2    Hardware Modeled by Memory    9
3.3    Proposed Method    11
3.3.1 Check Bit Correction    11
3.3.2 Illegal State Detection    13
3.3.3 Remapping Table (Output Correction)    14
3.4    Hardware Architecture    15
3.4.1 Check Bit Correction Module    16
3.4.2 Illegal State Detection Module    17
3.4.3 Approach Correspondence of the Memory Model and Hardware Implementation    22
3.5    Hardware Implementation Flow    22
3.6    Case Study 1: Traffic Light Controller    23
3.7    Case Study 2: Elevator Controller    24
Chapter 4 Experimental Results    28
4.1    Traffic Light Controller RTL Simulation    28
4.2    Elevator RTL Simulation    30
4.3    Gate-Level Overhead    31
4.4    Reliability Evaluation    32
Chapter 5 Conclusions and Future Work    39
5.1    Conclusions    39
5.2    Future Work    39
Bibliography    41

                                

[1] International Monetary Fund (IMF), “World Economic Outlook: Subdued Demand: Symptoms and Remedies,” Oct., 2016.
[2] U.S. Energy Information Administration (EIA), “International Energy Outlook 2016,” May 11, 2016.
[3] C.-W. Wu, "Symbiotic-System Approach for IOT Devices," in Proc. 25th IEEE Asian Test Symp. (ATS), Hiroshima, Nov. 2016 (McCluskey Keynote Speech).
[4] C.-W. Wu, B.-Y. Lin, H.-W. Hung, S.-M. Tseng, and Chi Chen. “Symbiotic System Models for Efficient IOT System Design and Test,” in Proc. 1st Int. Test Conference in Asia (ITC-Asia).
[5] B.-Y. Lin, H.-W. Hung, S.-M. Tseng, C. Chen, and C.-W. Wu, “Highly Reliable and Low-Cost Symbiotic IOT Devices and Systems,” in Proc. IEEE Int. Test Conf. (ITC), Fort Worth, Texas, Oct. 2017. (Invited)
[6] R. Bergamaschi, D. Brand, L. Stok, “Efficient Use of Large Don’t Cares in High-level and Logic Synthesis,” in Proc. International Conference on Computer-Aided Design (ICCAD), Nov 1995.
[7] M. Turpin. “The Dangers of Living with an X (bugs hidden in your Verilog).” In Proc. Synopsys Users Group (SNUG), 2003.
[8] L. Piper and V. Vimjam. “X-propagation woes: Masking bugs at RTL and unnecessary debug at the netlist,” in Proc. Design and Verification Conference (DVCon), 2012.
[9] P. K. Lala, Self-Checking and Fault-Tolerant Digital Design, CA, USA: Morgan Kaufmann, 2001.
[10] L.-T. Wang, C.-W. Wu, and X. Wen. VLSI Test Principles and Architectures: Design for Testability, Morgan Kaufmann, 2006.
[11] D. H. Yoon, M. Erez. “Memory Mapped ECC: Low-Cost Error Protection for Last Level Caches” in Proc. Int. Symp. Computer Architecture (ISCA), June, 2009.
[12] S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design, 3rd Edition, McGraw Hill.

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