記憶體的容錯設計在增進記憶體產量方面，扮演著重要的腳色。為了達到提升可靠度的目的，有許多的方法被提出。而其中最廣泛為人所利用的技術之一，是以插入在記憶體中的冗餘記憶體來取代有瑕疵的記憶體單元。現今，雷射切割技術因為可以加強冗餘記憶體之使用效益，因此對於記憶體的產能有著提升的作用。然而，切割點的選擇明顯地影響到冗餘記憶體的利用率。不佳的切割點甚至是沒有作用的。為了解決這個問題，本篇論文提出兩個演算法。第一個演算法是使用於找出適當的切割點。此演算法修正了一些以前演算法的錯誤，並提出一個較為完善的方法來搜尋切割點。另外，因為大部分的啟發式求解演算法在記憶體被切割的狀況下無法正確運作，因此，為了得知錯誤樣本是否可以被修復，我們提出了第二個演算法，命名為Modification of Most-Repair (MMR). 實驗結果顯示我們提出的演算法在可靠度上有所提升，並且能更有彈性的運用冗餘記憶體。

Fault-tolerant design for memory production is getting to play an important role in increasing the yield rate of manufacturing. To improve the reliability of memory manufacturing, there are many methods that have been proposed. One of the most used technologies is replacing the faulty cells with spare memory interleaved in the memory. Nowadays, the laser cutting technology improves the yield of memories because of the enhancement of the use of spare lines. However, the issue of choosing a cutting location significantly affects the utilization of spare lines. A bad cutting location can even render it useless. This thesis presents two algorithms to solve this problem. The first one is designed to seek out a good cutting location. It corrects some defects of previous algorithms and provides a better approach to find cutting candidates. In addition, because most heuristic solution-finding algorithms do not work properly under the condition of cutting memory, the second algorithm, called Modification of Most-Repair (MMR) is proposed to help make the decision as to whether or not a solution exists for the faulty pattern. The experimental results show that our proposed algorithms improve the reliability of memory manufacturing and the flexibility of spare lines.

[1]L. Youngs and S. Paramanandam, “Mapping and Repairing Embedded-Memory Defects,” IEEE Design and Test of Computers, vol. 14, issue 1, pp.18-24, January 1997.

[2]J. I. Raffel, A. H. Anderson, G. H. Chapman, K. H. Konkle, B. Mathur, A. M. Soares, and P. W. Wyatt, “A Wafer-Scale Digital Integrator Using Restructurable VLSI,” IEEE Journal of Solid-State Circuits, vol. 20, pp.399-406, February 1985.

[3]Y. Ueoka, C. Minagawa, M. Oka, and A. Ishimoto, “A Defect-Tolerant Design for Full-Wafer Memory LSI,” IEEE Journal of Solid-State Circuits, vol. 19, pp.319-324, June 1984.

[4]J. R. Day, “A Fault-Driven Comprehensive Redundancy Algorithm for Repair of Dynamic RAMs,” IEEE Design and Test of Computers, vol. 2, issue 3, pp.35-44, 1985.

[5]I. Kim, Y. Zorian, G. Komoriya, H. Pham, F. P. Higgins, and J. L. Lewandowski, “Built in Self Repair for Embedded High Density SRAM,” Proceedings on International Test Conference (ITC 1998), Washington D C, USA, pp.1112-1119, October 1998.

[6]T. W. Tseng, J. F. Li, C. C. Hsu, A. Pao, K. Chiu, and E. Chen, “A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs,” Proceedings on IEEE International Test Conference 2006 (ITC 2006), Santa Clara, CA, pp.1-9, October 2006.

[7]J. F. Li, J. C. Yeh, R. F. Huang, and C. W. Wu, “A Built-In Self-Repair Design for RAMs with 2-D Redundancy,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, issue 6, pp.742-745, June 2005.

[8]B. A. Izadi, and F. Ozguner, “Enhanced Cluster k-Ary n-Cube, A Fault-Tolerant Multiprocessor,” IEEE Transactions on Computers, vol. 52, issue 11, pp.1443-1453, November 2003.

[9]M. Choi, N. Park, V. Piuri, F. Lombardi, “Reliability Measurement of Mass Storage System for Onboard Instrumentation,” IEEE Transactions on Instrumentation and Measurement, vol. 54, issue 6, pp.2297-2304, December 2005.
[10]N. Hasan, and C.L. Liu, “Minimum Fault Coverage in Reconfigurable Arrays,” Proceedings of Eighteen International Symposium on Fault-Tolerant Computing (FTCS-18), Tokyo, Japan, pp.348-353, June 1988.

[11]S. Y. Kuo, and W. K. Fuchs, “Efficient Spare Allocation in Reconfigurable Arrays,” Proceedings on 23rd Conference on Design Automation (DAC 1986), Las Vegas, Nevada, USA, pp.385-390, June 1986.

[12]F. Yu, C. H. Tsai, Y. W. Huang, H. Y. Lin, D. T. Lee, and S. Y. Kuo, “Efficient Exact Spare Allocation Via Boolean Satisfiability,” Proceedings of 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2005), Geneva, Switzerland, pp.361-370, October 2005.

[13]S. Y. Kuo, and W. K. Fuchs, “Modelling and Algorithms for Spare Allocation in Reconfigurable VLSI,” Proceedings of IEEE Computers and Digital Techniques, vol. 139, issue 4, pp.323-328, July 1992.

[14]H. C. Liang, W. C. Ho, and M. C. Cheng, “Identify Unrepairability to Speed-Up Spare Allocation for Repairing Memories,” IEEE Transactions on Reliability, vol. 50, issue 2, pp.358-365, June 2005.

[15]W. Che, and I. Koren, “Fault Spectrum Analysis for Fast Spare Allocation in Reconfigurable Arrays,” IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT 1992), Dallas, Texas, USA, pp.60-69, November 1992.

[16]Y. Y. Chen, and S. J. Upadhyaya, “Reliability, Reconfiguration, and Spare Allocation Issues in Binary-tree Architectures Based on Multiple-level Redundancy,” IEEE Transactions on Computers, vol. 42, issue 6, pp.713-723, June 1993.

[17]H. Y. Lin, F. M. Yeh, and S. Y. Kuo, “An Efficient Algorithm for Spare Allocation Problems,” IEEE Transactions on Reliability, vol. 5, issue 2, pp.369-378, June 2006.

[18]H. Yamaguchi, M. Hongo, T. Miyauchi, and M. Mitani, “Laser Cutting of Aluminum Stripes for Debugging Integrated Circuits,” IEEE Journal of Solid-State Circuits, vol. 20, issue 6, pp.1259-1264, December 1985.

[19]Y. N. Shen, N. Park, and F. Lombardi, “Spare Cutting Approaches for Repairing Memories,” Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD 1996), Austin, Texas, USA, pp.106-111, October 1996.

[20]N. Park and F. Lombardi, “Repair of Memory Arrays by Cutting,” Proceedings of International Workshop on Memory Technology, Design and Testing (MTDT1998), San Jose, California, USA, pp.124-130, August 1998.

[21]M. Tarr, D. Boudreau, and R. Murphy, “Defect Analysis System Speeds Test and Repair of Redundant Memories,” Electronics, vol. 57, no. 1, pp.175-179, January 1984.

[22]H. Y. Lin, H. Z. Chou, F. M. Yeh, I. Y. Chen, and S. Y. Kuo, “An Efficient Algorithm for Reconfiguring Shared Spare RRAM,” Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD 2004), San Jose, California, USA, pp.544-546, October 2004.

[23]H. Y. Lin, F. M. Yeh, I. Y. Chen, and S. Y. Kuo, “An Efficient Perfect Algorithm For Memory Repair Problems,” Proceedings of 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI System (DFT 2004), Cannes, France, pp.306-311, October 2004.

[24]D. K. Bhavsar, “An Algorithm for Row-Column Self-Repair of RAMs and Its Implementation in the Alpha 21264,” Proceedings on International Test Conference (ITC 1999), Atlantic City, NJ, USA, pp.311-318, September 1999.

[25]C. P. Low and H. W. Leong, “A New Class of Efficient Algorithms for Reconfiguration of Memory Arrays,” IEEE Transactions on Computers, vol. 45, issue 5, pp.614-618, May 1996.

[26]C. P. Low and H. W. Leong, “Minimum Fault Coverage in Memory Arrays: A Fast Algorithm and Probabilistic Analysis,” IEEE Transactions on Computer – Aided Design of Integrated Circuits and Systems, vol. 15, issue 6, pp.681-690, June 1996.

[27]W. K. Huang, and Y. N. Shen, and F. Lombardi, “New Approaches for The Repairs of Memories with Redundancy by Row/Column Deletion for Yield Enhancement,” IEEE Transactions on Computer – Aided Design of Integrated Circuits and System, vol. 9, issue 3, pp.323-328, March 1990.

[28]F. Lombardi and W. K. Huang, “Approaches for the Repair of VLSI/WSI RRAMs by Row/Column Deletion,” Proceedings of Eighteen International Symposium on Fault-Tolerant Computing (FTCS-18), Tokyo, Japan, pp.342-347, June 1988.

[29]R. L. Hadas and C.L. Liu, “Fast Search Algorithms for Reconfiguration Problems,” Proceedings of IEEE International Workshop on Defect and Fault Tolerance in VLSI System (DFT 1991), pp.260-273, November 1991.

[30]D. M. Blough and A. Pelc, “A Clustered Failure Model for the Memory Array Reconfiguration Problem,” IEEE Transactions on Computers, vol. 42, issue 5, pp.518-528, May 1993.

[31]D. M. Blough, “Performance Evaluation of A Reconfiguration Algorithm for Memory Arrays Containing Clustered Faults,” IEEE Transactions on Reliability, vol. 45, pp.274-284, June 1996.

[32]J. Chen and I. A. Kanj, “Constrained Minimum Vertex Cover in Bipartite Graphs: Complexity and Parameterized Algorithms,” Journal of Computer and System Science, vol. 67, issue 4, pp.833-847, December 2003.

[33]H. Fernau, and R. Niedermeier, “An Efficient Exact Algorithm for Constraint Bipartite Vertex Cover,” Journal of Algorithms, vol. 38, issue 2, pp.374-410, February 2001.

[34]R. W. Haddad, A. T. Dahura, and A.B. Sharma, “Increased Throughput for the Testing and Repair of RAMs with Redundancy,” IEEE Transactions on Computers, vol. 40, issue 2, pp.154-166, February 1991.

[35]N. Funabiki and Y. Takefuji, “A Parallel Algorithm for Allocation of Spare Cells on Memory Chips,” IEEE Transactions on Reliability, vol. 40, issue 3, pp.338-346, August 1991.

[36]W. Shi and W. K. Fuchs, “Probabilistic Analysis and Algorithms for Reconfiguration of Memory Arrays,” IEEE Transactions on Computer – Aided Design, vol. 11, issue 9, pp.1153-1160, September 1992.

[37]S. Y. Kuo, and I. Y. Chen, “Efficient Reconfiguration Algorithms for Degradable VLSI/WSI Arrays,” Proceedings of 3rd International Conference on Wafer Scale Integration (ICWSI 1991), San Francisco, California, USA, pp.120-126, January 1991.

[38]P. L. Chor, “An Efficient Reconfiguration Algorithm for Degradable VLSI/WSI arrays,” IEEE Transactions on Computers, vol. 49, issue 6, pp.553-559, June 2000.

[39]C. T. Huang, C. F. Wu, J. F. Li, and C. W. Wu, “Built-In Redundancy Analysis for Memory Yield Improvement,” IEEE Transactions on Reliability, vol. 52, issue 4, pp.386-399, December 2003.