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研究生： 古什尼
Gude, Srinivas
論文名稱： 應用多重延遲訊號消除濾波器於電網嚴峻情況下之先進鎖相迴路技術
ADVANCED PHASE-LOCKED LOOPS BASED ON MULTIPLE DELAYED SIGNAL CANCELLATION FILTERS UNDER ADVERSE GRID CONDITIONS
指導教授： 朱家齊
Chu, Chia-Chi
口試委員: 吳財福
WU, TSAI-FU
洪穎怡
Hong, Yin–Yi
賴炎生
Lai, Yen-Shin
吳有基
Wu, Yu-Chi
林法正
Lin, Faa-Jeng
連國龍
Lian, Kuo-Lung
邱煌仁
Chiu, Huang-Jen
張文恭
Chang, Gary W
學位類別： 博士
Doctor
系所名稱： 教務處 - 跨院國際博士班學位學程
International Intercollegiate PhD Program
論文出版年： 2018
畢業學年度： 106
語文別： 英文
論文頁數： 101
中文關鍵詞： 併網技術 、相角 、頻率 、振福 、諧波 、串連延遲訊號消除 、多重延遲訊號消除 、鎖相迴路
外文關鍵詞： Grid synchronization, Phase-angle, Frequency, Amplitude, Harmonics, Cascaded delayed signal cancellation (CDSC), Multiple delayed signal cancellation (MDSC), Phase-locked loops (PLLs)
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    • 於分散式再生能源發電系統併網技術中，電網併接點之三相電壓振幅、相角、與頻率，是同步併網控制的關鍵資訊。目前最廣泛使用之方式為鎖相迴路技術。理論上，同步參考框之鎖相迴路與增強型鎖相迴路技術，因為其結構簡單且發展已趨完備，已經廣泛應用。但隨著電網中電力電子式負載的激增，電網之電壓因此會產生嚴重之三相不平衡與諧波失真等現象。於此嚴峻的電網電壓條件下，鎖相迴路的頻寬必須增加，以改善其濾波能力，並須確保系統之快速動態響應。鎖相迴路使用的濾波器，可內嵌於鎖相迴路中，或前饋於鎖相迴路之輸入信號。本文提出一種用於鎖相迴路之新穎濾波技術，稱為多重延遲訊號消除法，可用於產生(i)靜止參考框中電網電壓的基頻正序分量，(ii)同步參考框中電網電壓的直流分量，與(iii)單相系統之選擇性諧波成分。多重延遲訊號消除濾波器具有更大的設計彈性，可消除不需要的諧波成分。與近來所提出之串聯延遲信號消除濾波器相較，可減少延遲時間，並且同時兼具並聯延遲信號消除濾波器與移動平均濾波器的優點，並減少的數位實現下之計算複雜度。本文探討設計多重延遲訊號消除濾波器，應用於再生能源發電系統併網之鎖相迴路技術，包含以下四項:(i)三相同步參考框鎖相迴路的前饋濾波形式多重延遲訊號消除濾波器設計，(ii)三相同步參考框鎖相迴路之遞迴型式多重延遲訊號消除濾波器設計，(iii)三相增強型鎖相迴路之內嵌式多重延遲訊號消除濾波器設計，與(iv)增強型鎖相迴路之單相多重延遲訊號消除濾波器設計。最後以即時模擬與實驗室硬體平台，進行模擬驗證其準確性。與其他進階鎖相迴路相較，所提出多重延遲訊號消除濾波器，可提供較快速與精準的動態響應。

    The phase angle, frequency, and amplitude of grid voltage are the crucial information for the control and grid synchronization of grid-connected power electronic systems utilized in distributed generators. The conventional approach for the estimation of phase angle, frequency, and amplitude is to explore phase-locked loop techniques. In theory, synchronous reference frame (SRF) phase-locked loop (PLL) and enhanced phase-locked loop (EPLL) are the most conventional and widely used in power engineering applications because of their simple structure and robust features for digital implementation. With the proliferation of power electronic loads in the power grid, the grid voltage has unbalances and harmonic distortions. Under these severe conditions of the grid voltage, the bandwidth of the PLLs has to compromise between filtering capability and dynamic responses. The PLL dynamic performance can be improved by using in-loop filter or pre-filter. This thesis proposes novel filtering techniques based on multiple delayed signal cancellation (MDSC). These filtering techniques can be utilized for extracting (i) fundamental frequency positive sequence (FFPS) component of the grid voltage in stationary reference frame, (ii) dc component of
    the grid voltage in the synchronous reference frame, and (iii) selected harmonic component in single phase applications. The proposed MDSC filters have more flexibility to configure the lowest undesired harmonics and hence they can have less delay time when compared to the cascaded delayed signal cancellation (CDSC) filters for the same harmonic elimination capability. These filters can have combined advantages of both CDSC filters and moving average filters (MAFs) in their recursive implementations. For example, similar to CDSC filters, the MDSC filters can have more flexibility to configure the delay time introduced by the filters. In addition, similar to MAFs, the MDSC filters can provide less computational burden. In this thesis, advanced PLLs based on MDSC filters are proposed. They are (i) pre-filtered direct-form MDSC filters based three-phase SRF-PLL, (ii) recursive-form MDSC filters based three-phase SRF-PLLs, (iii) in-loop MDSC filters based three-phase enhanced PLL, and (iv) single-phase MDSC filters based enhanced PLL. Experimental verifications demonstrate the effectiveness of the proposed PLLs and provide good dynamic responses when compared to the recent advanced PLLs.

    1 Introduction 1 1.1 Background and Motivation 1 1.2 MDSC filters for the SRF-PLL as a pre-filtering stage 3 1.3 Recursive-form MDSC filters based SRF-PLL 4 1.4 MDSC filters based three-phase EPLL 5 1.5 Single-phase MDSC filters based EPLL 6 2 MDSC Filters and Their Application as a Pre-filtering Stage to SRF-PLL 2.1 DSC, GDSC, and MDSC 8 2.1.1 Space Phasor Notations 8 2.1.2 DSC and GDSC 10 2.1.3 MDSC 12 2.1.4 Extensions 17 2.1.5 Relationships with Other Operators 18 2.1.6 Discrete Implementations 19 2.2 MDSC-Based PLLs 20 2.2.1 PI Control Design 22 2.2.2 Frequency Adaptation Scheme 23 2.2.3 Stability of the MDSC-FF 26 2.2.4 Stability of the Frequency Adaptive MDSC Pre-Filtered PLL 27 2.3 Experimental Verifications 29 2.4 Discussion 34 3 Recursive-form MDSC Filters Based SRF-PLLs 35 3.1 Recursive-Form of MDSC Operators 35 3.1.1 Grid Voltage Representations 35 3.1.2 Recursive Forms of dq-Frame MDSC Operators 37 3.1.3 Recursive Forms of ab -Frame MDSC Operators 39 3.1.4 Complexity of Recursive-Form MDSC Operators 41 3.2 Pre-filtered recursive-form MDSC-PLL 41 3.2.1 Corrections in amplitude and phase-angle of the recursive-form MDSC-PLL 42 3.2.2 Stability Analysis and Design Guidelines 44 3.3 In-Loop Filtered Recursive-Form MDSC-PLL 46 3.3.1 Approximated Transfer Function of dq-Frame MDSC Operators 46 3.3.2 Loop Filter Design 47 3.4 Experimental Verifications 49 3.5 Discussion 52 4 MDSC Filters Based Three-phase Enhanced PLL 4.1 Overview of 3P-EPLLs 54 4.1.1 3P-EPLL 55 4.1.2 CDSC Filter-Based 3P-EPLL 57 4.2 MDSC-Filter-Based 3P-EPLL 60 4.2.1 MDSC Filters 61 4.2.2 Features of MDSC Filters 63 4.2.3 Recursive-Form Implementation of MDSC filter 66 4.2.4 MDSC-3P-EPLLs 67 4.3 Simulations and Experimental Verifications 73 4.3.1 Simulation results 76 4.3.2 Experimental Results 77 4.4 Discussion 80 5 Single-phase MDSC Filters and Their Application to Enhanced PLL 5.1 Single phase MDSC Filters 81 5.1.1 MDSC Operations 81 5.1.2 Special Feature 84 5.1.3 Comparisons With Other Operators 85 5.2 Applications to Enhance PLLs 86 5.3 Experimental Verifications 88 5.3.1 Test Case I: Voltage sag distortions 90 5.3.2 Test Case II: Phase jump distortions 90 5.3.3 Test Case III: Frequency jump with voltage sag 90 5.4 Discussion 91 6 Conclusions 92 References 94

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