利用金屬濕蝕刻後製程於新型CMOS-MEMS三軸加速度計之開發

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研究生：	蔡明翰 Tsai, Ming-Han
論文名稱：	利用金屬濕蝕刻後製程於新型CMOS-MEMS三軸加速度計之開發 Design and Implementation of CMOS-MEMS Tri-axis Accelerometers Using Metal Wet-etching Process
指導教授：	方維倫 Fang, Weileun
口試委員:	張培仁 Chang, Pei-Zen 盧向成 Lu, Michael S.-C 李昇憲 Lee, Sheng-Shian 謝哲偉 Hsieh, Jerwei 吳名清 Wu, Ming-Chin
學位類別：	博士 Doctor
系所名稱：	工學院 - 奈米工程與微系統研究所 Institute of NanoEngineering and MicroSystems
論文出版年：	2012
畢業學年度：	100
語文別：	中文
論文頁數：	138
中文關鍵詞：	金屬濕蝕刻、三軸加速度計
外文關鍵詞：	metal wet-etching, 3-axis accelerometer
相關次數：	點閱：3 下載：0
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本研究以標準CMOS製程與金屬濕蝕刻後製程來設計並製造三軸加速度計，以往在學術界所提出之CMOS-MEMS元件大多使用乾蝕刻製程為主，其結構設計以及後製程線寬受限於製程方法而僅能有平面方向的結構設計，本研究提出一金屬濕蝕刻後製程與元件設計方法，除了可輕易定義平面方向的幾何形狀外，亦可選擇性的底切任一金屬層，因此本製程在結構設計上相對於乾蝕刻僅能定義深度方向具有更高之靈活性，並且此製程能夠充分利用CMOS製程的極小線寬優勢作為電容感測之間隙，可充分提高感測電容的大小，進而提升元件之靈敏度。本研究首先利用結構獨立之同平面與出平面加速度計設計來驗證此製程之可行性，藉由極小線寬以及良好底切的蝕刻能力，使得此加速度設計能夠有遠高於一般乾蝕刻加速度計的元件效能，接下來更進而利用此製程提出兩種不同之三軸單一質量塊加速度計設計，根據其整合方式可分為平面式整合與垂直式整合，平面式整合利用其濕蝕刻線寬優勢將三軸感測電極整合在單一質量塊周圍，其結構尺寸僅有500x500um2；垂直式整合則是利用多層薄膜之特色同時整合同平面與出平面電極於單一電極結構上，同時其感測方式依然能夠為氣密閉合與全差分之架構，由於垂直整合感測電極的設計，三軸感測電極的數量不會隨著元件面積縮小而減少，因此元件能夠維持與單軸加速度計相同，而其結構面積更能夠縮小至400x400um2之等級，本研究所提出之加速度計結構尺寸不僅能與現有商品化之加速度計競爭，使CMOS-MEMS加速度計具有更高的成本競爭力。

This thesis based on the standard CMOS process and post CMOS metal wet-etching process to design and implement 3-axis CMOS-MEMS accelerometers. Typical CMOS-MEMS devices in academia typically adopted dry-etching process for structure geometry define and release. The design can only planar geometry and line width capabilities are restricted by the post CMOS process. This study proposed a design methodology using post CMOS metal wet-etching process. In addition to easily define the planar geometry, the undercut of metal layers is also achievable. Thus, higher design flexibility for CMOS-MEMS devices is achieved. Moreover, this process can fully utilize the CMOS line width to enhance the performance of CMOS-MEMS capacitive devices.
Firstly, a metal wet-etching based CMOS-MEMS in-plane and out-of-plane accelerometers are designed to verify the feasibility of this process. Using the small line width of CMOS process and the thickness of metal layer as capacitive sensing gap, the metal wet-etching based accelerometers have ultra-high performance compared with dry-etching ones. This study also proposed planar and vertical integration method to reduce the chip size. Planar integration design takes advantage of the line width ability to integrate the 3-axis sensing electrodes around the proof mass. Vertical integration method utilize the feature of multi-layer stacking of CMOS process to integrate the in-plane and out-of-plane sensing electrodes vertically. Moreover, the sensing scheme can still be the fully-differential and gap-closing sensing types. The structure area is significantly reduced but the number of sensing electrodes is still maintained.

第一章    序論    1
1-1    前言    1
1-2    文獻回顧    2
1-2.1    微機電加速度計感測型態    2
1-2.2    微機電電容式加速度計製程分類    5
1-2.3    CMOS-MEMS製程分類    8
1-3    研究動機與目的    9
第二章 加速度計原理與分析    22
2-1    單軸加速度計機械結構操作原理    22
2-2    機械與電路介面    26
2-3    電容感測電路架構與雜訊分析    28
2-4    機電系統整合之暫態與穩態分析    29
第三章 濕蝕刻三軸加速度計    39
3-1    濕蝕刻三軸加速度計結構設計與模擬    39
3-1.1    質量塊設計    39
3-1.2    彈簧設計    40
3-1.3    感測電極設計與模擬    40
3-2    全差分感測架構設計    41
3-3    製程流程與結果    42
3-4    元件性能量測與討論    44
3-5    總結    45
第四章 平面整合型態之三軸加速度計    60
4-1 平面整合之三軸加速度計設計與模擬    60
4-1.1 質量塊設計    60
4-1.2 三軸彈簧設計    61
4-1.3 三軸感測電極設計    61
4-2 平面整合三軸加速度計製造    62
4-3平面整合三軸加速度計量測與分析    63
4-4 總結    65
第五章 垂直整合之三軸加速度計    76
5-1 加速度計結構設計與模擬    76
5-1.1 質量塊設計    76
5-1.2 三軸彈簧設計    77
5-1.3 三軸感測電極設計    78
5-1.4 三軸全差分感測與解耦合設計    79
5-2 垂直整合三軸加速度計之製程流程    82
5-3 元件性能量測與討論    83
5-4 總結    85
第六章 成果總結與未來研究方向    98
參考文獻    102
附錄A：低熱變形加速度計設計    111
A-1低熱變形CMOS-MEMS加速度計    111
A-2 低熱變形CMOS-MEMS加速度計結構設計    112
A-3 低熱變形CMOS-MEMS加速度計熱變形模擬    113
A-4 製程流程與量測結果    114
A-5 加速度計與封裝設計之整合    115
附錄B 晶圓級低溫氣密封裝設計    125
B-1 微機電加速度計封裝技術    125
B-2 金屬密封封裝設計與模擬    126
B-3 製程流程與結果    128
論文發表    139
 
圖目錄
圖1-1 微機電元件發展流程與應用    11
圖1-2典型電容式加速度計感測方式示意圖[22]    12
圖1-3 壓阻式加速度計剖面圖[23]    12
圖1-4 壓電式加速度計剖面圖[24]    12
圖1-5熱感式加速度計[25]    13
圖1-6穿隧式加速度計剖面圖 [19-20]    13
圖1-7振動式加速度計[21]    13
圖1-8 (a) 垂直式加速度計之感測架構；(b)側向式加速度計之感測架構 [32]    14
圖1-9 利用梳狀電極感測出平面加速度產生的電容變化 [40]    14
圖1-10 扭轉的結構下擺放感測電極以感測出平面訊號 [43]    14
圖1-11 Sandia’s iMEMS (MEMS-First)製程 [50]    15
圖1-12 ADI之三軸獨立結構加速度計晶片[51]    15
圖1-13 Sandia’s iMEMS製程之單一質量塊之三軸加速度計[52]    16
圖1-14 透過EDP蝕刻液將為高濃度參雜之單晶矽移除之製程步驟[53]    16
圖1-15 以扭轉方式感測出平面方向的加速度元件設計[53]    16
圖1-16 以全對稱結構之單晶矽加速度計元件 [54]    17
圖1-17 多晶矽回填技術所研製的出平面感測加速度計製程[54]    17
圖1-18 以全對稱結構之單晶矽加速度計元件實體圖 [54]    18
圖1-19 以多晶矽回填技術之三軸方向加速度感測系統架構[55]    18
圖1-20 三軸方向加速度感測系統架構實體圖[55]    19
圖1-21 以SOI製程達成三軸加速度感測之架構 [56]    19
圖1-22 出平面方向差分電極之設計 [57]    19
圖1-23以SOI晶片研製三軸方向皆差分電極設計[60]    20
圖1-24 SiTime使用前段製程之振盪器[73]    20
圖1-25 Analog Device使用中段製程之加速度計[74]    20
圖1-26 後CMOS製程流程圖 [75]    21
圖2-1 加速度計模型圖    32
圖2-2 模型運動時受力圖    33
圖2-3 不同阻尼比之運動型態圖    33
圖2-4 典型共振頻譜圖    34
圖2-5 電容感測示意圖    34
圖2-6 放大因子與操作頻率關係圖    34
圖2-7 單端感測架構示意圖    35
圖2-8 差分感測架構示意圖I    35
圖2-9 差分感測單端輸出架構示意圖II    36
圖2-10 全差分感測架構示意圖    36
圖2-11 完整系統架構圖    37
圖2-12 機電介面架構示意圖    37
圖2-13 不同Q值狀況的起始暫態響應圖    38
圖2-14 在不同頻率下電壓差異造成穩態震盪圖    38
圖3-1 三軸加速度計設計示意圖    47
圖3-2 質量塊設計剖面圖    48
圖3-3 彈簧設計概念上視圖    48
圖3-4 彈簧接點與剖面圖    49
圖3-5 感測電極設計示意圖    49
圖3-6 同平面感測電極模擬圖    50
圖3-7 出平面電極蝕刻示意圖    50
圖3-8 同平面加速計全差分繞線示意圖    51
圖3-9 出平面加速度計全差分架構繞線示意圖    51
圖3-10 濕蝕刻引洞設計圖    52
圖3-11 製程流程圖    53
圖3-12 製程結果SEM圖    54
圖3-13 同平面加速度計SEM圖    54
圖3-14 濕蝕刻同平面感測臂剖面圖    55
圖3-15 出平面加速度計SEM圖    55
圖3-16 製程結果光學顯微鏡觀察圖    56
圖3-17 同平面共振頻率量測    56
圖3-18 出平面共振頻率量測圖    57
圖3-19 (a)元件封裝與印刷電路版 (b)量測架設示意圖    57
圖3-20 頻譜分析儀輸出訊號圖    58
圖3-21 (a)同平面加速度計(b)出平面加速度計性能量測圖    58
圖3-22 10mG加速度量測    59
圖4-1 平面整合之三軸加速度計結構示意圖    66
圖4-2 改良面積使用率之設計概念圖    66
圖4-3 彈簧剛性模擬結果圖    67
圖4-4 模態模擬圖    67
圖4-5 感測電極剖面圖    68
圖4-6 同平面與出平面感測電容模擬圖    68
圖4-7 製程流程圖    69
圖4-8 小線寬濕蝕刻設計示意圖    70
圖4-9 平面整合三軸加速度計製程結果圖    70
圖4-10 製程結果圖    71
圖4-11 出平面電極翹曲量測圖    71
圖4-12 同平面電極翹曲量測圖    72
圖4-13 遠離彈簧處之同平面電極翹曲圖    72
圖4-14 接近彈簧處之同平面電極翹曲圖    73
圖4-15 封裝與量測架設圖    73
圖4-16 頻譜量測示意圖    74
圖4-17 X方向感測訊號量測圖    74
圖4-18 Y方向感測訊號量測圖    75
圖4-19 Z方向感測訊號量測圖    75
圖5-1 0.18m CMOS 製程堆疊圖    87
圖5-2 垂直整合三軸加速度計結構示意圖    87
圖5-3 三軸彈簧結構示意圖    88
圖5-4 三軸彈簧剛性模擬圖    88
圖5-5 AA’結構剖面圖    89
圖5-6 BB’ 結構剖面圖    89
圖5-7 感測電容模擬圖    89
圖5-8 同平面全差分感測示意圖    90
圖5-9 出平面全差分感測示意圖    90
圖5-10 出平面加速度耦合至同平面電極感測圖    90
圖5-11同平面加速度互相耦合示意圖    91
圖5-12 同平面與出平面耦合示意圖    91
圖5-13 製程流程圖    92
圖5-14 製程結果SEM圖    93
圖5-15 感測電極剖面SEM圖    93
圖5-16 質量塊翹曲圖    94
圖5-17 感測電極重疊面積量測圖    94
圖5-18 同平面共振頻率量測圖    94
圖5-19 出平面共振頻率圖    95
圖5-20 元件簡易封裝圖    95
圖5-21 量測架設示意圖    95
圖5-23 X方向訊號量測圖    96
圖5-24 Y方向訊號量測圖    96
圖5-25 Z方向訊號量測圖    97
圖5-26 起始電容非對稱示意圖    97
圖6-1 加速度計與壓力計整合示意圖    101
圖6-2 加速度計與穿矽導線整合示意圖    101
圖A-1 多層懸臂樑受熱變形模擬圖    117
圖A-2 典型與純二氧化矽結構剖面示意圖    117
圖A-3 彈簧結構設計示意圖    118
圖A-4 彈簧受熱變形模擬圖    118
圖A-5 彈簧質量塊受熱變形模擬圖    119
圖A-6 製程流程圖    120
圖A-7 製程SEM圖(a)(b)二氧化矽結構與(c)(d)多層膜結構加速度計    121
圖A-8 (a)純二氧化矽結構，(b)多層膜結構受熱表面形貌量測圖    122
圖A-9 加速度計受1G加速度時頻譜分析圖    123
圖A-10 加速度與輸出電壓量測圖    123
圖A-11 製程整合流程圖    124
圖B-1 微機電加速度計封裝剖面圖[94]    130
圖B-2 epoxy 封裝製程流程    130
圖B-3 玻璃膏接合介面SEM圖[94]    131
圖B-4 共晶結合比例與溫度之關係圖[95]    131
圖B-6 保護層受封裝壓力便行模擬圖    132
圖B-7 支撐位置設計示意圖    132
圖B-8 整體封裝示意圖    133
圖B-9 製程流程圖    134
圖B-10 製程完成SEM圖    135
圖B-11 移除封裝薄膜SEM圖    135
圖B-12 封裝薄膜之支撐結構SEM圖    136
圖B-13 封裝薄膜內部橋狀結構SEM圖    136
圖B-14 製程完成薄膜表面形貌量測圖    137
圖B-15 表面濺鍍2m鋁後的表面形貌圖    137
圖B-16 封孔狀況SEM圖    137
圖B-17 剛性量測結果圖    138

 
表目錄
表2-1 電路規格表    32
表3-1 彈簧剛性公式表    46
表3-2 彈簧剛性模擬結果表    46
表3-3 量測結果表    46
表3-4 效能比較表    47
表5-1 量測結果與比較表    86
表A-1 CMOS製程材料熱膨脹係數與密度表    116
表A-2 加速度計量測結果與比較表    116

                                

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