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研究生: 陳哲偉
Chen, Che-Wei
論文名稱: 製作鋁/氧化鑭/金奈米晶體/二氧化矽/p型矽快閃記憶體
Fabrication of Al/LaxO1-x/Gold Nanocrystal/SiO2/p-Si Flash Memory
指導教授: 葉鳳生
Yeh, Fon-Shan
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2010
畢業學年度: 98
語文別: 中文
論文頁數: 107
中文關鍵詞: 金奈米晶體浸鍍法高介電材料
外文關鍵詞: gold nanocrystal, immersion plating, high-k material
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  • 本實驗提出一種簡單、低成本且高產量的浸鍍法(immersion plating)製作金奈米晶體(gold nanocrystal),並完成金氧半電容(MOSC)結構的非揮發記憶體。在沉積金奈米晶體後快速熱退火為了改善金粒與矽的介面。以氧化鑭當作控制介電層,藉以提升寫入/抹除速度,
    利用高溫氧化法在矽上成長二氧化矽當作穿遂氧化層,厚度為5、7奈米,接著低壓沉積非晶矽,厚度為2奈米,此層作為浸鍍法行氧化還原反應時矽原子的來源,浸鍍液成分為四氯化金酸/氫氟酸濃度為0.48mM/1.5mM,浸鍍時間3秒鐘,金奈米晶體於矽表面還原形成,以掃描式電子顯微鏡和穿透式電子顯微鏡觀察金粒尺寸及密度。
    對於控制介電層,氧化鑭厚度20、30奈米由電子槍蒸鍍後回火400度時間10分鐘,蒸鍍鋁後,形成鋁/氧化鑭/金奈米晶體/二氧化矽/p型矽結構,氧化鑭(20奈米)配合二氧化矽(7奈米)和氧化鑭(30奈米)配合二氧化矽(5奈米),由電容-電壓量測來決定寫入抹除特性。為了改善慢的抹除速度,沉積金奈米晶體後快速熱退火200度30分鐘,由電流-電壓的特性,討論穿遂電流機制,發現在小電場(0~8MV/cm)時主要為直接穿遂,大電場(9~13MV/cm)時為F-N穿遂主導,發現穿遂電流有明顯提升,RTA製程改善寫入抹除速度。氧化鑭(30奈米)/二氧化矽(5奈米)此厚度條件下,在104秒後仍有1.1伏的retention特性,在103次寫入抹除週期後仍有2.1伏的endurance特性。


    英文摘要……………………………………………………………………………….i 中文摘要……………………………………………………………………………...iii 目錄………………………………………………………………………………...…vi 圖片索引…………………………………………………………………………….viii 表格索引…………………………………………………………………………......xv 第一章 序論………………..…………………………………1 第二章 記憶體元件及操作原理…………………………..…8 2.1 SONOS 非揮發性記憶體…………………………………..…..8 2.2 非揮發性記憶體的寫入/抹除機制……………………………15 2.3 非揮發記憶體可靠度………………………………………….22 2.4.1 retention…………………………………………………..22 2.4.2 endurance…………………………………………………22 第三章 實驗…………………………………………………24 3.1 實驗設計……………………………………………………….24 A 奈米金粒製作……………………………………………….24 B 二氧化矽薄膜及厚度設計………………………………….25 C 氧化鑭的製作及厚度設計………………………………….25 3.2 金奈米晶體記憶體元件製作………………………………….28 3.2.1 Al/SiO2(30 nm)/AuNCs/SiO2(7 nm)/p-Si(Run 9)結構的 製作…………………………………………………………28 3.2.2 Al/LaxO1-x/AuNCs/SiO2/p-Si 結構的製作…………..……28 -Al/LaxO1-x(20 nm)/AuNCs/SiO2(7 nm)/p-Si (Run 10) -Al/LaxO1-x(20 nm)/AuNCs/SiO2(7 nm)/p-Si (Run 14) -Al/LaxO1-x(30 nm)/AuNCs/SiO2(5 nm)/p-Si (Run 12) -Al/LaxO1-x(30 nm)/AuNCs/SiO2(5 nm)/p-Si (Run 13) -Al/LaxO1-x(20 nm)/AuNCs/SiO2(5 nm)/p-Si (Run 15) 3.3 量測分析……………………………………………………….35 3.3.1 材料量測分析……………………………………………35 -SEM -TEM -AFM 3.3.2 電性量測分析……………………………………………35 3.3.2-1 C-V量測………………………………………….35 3.3.2-2 retention 量測…………………………………….36 3.3.2-3 endurance 量測…………………………………..37 3.3.2-4 I-V量測……………………………………………37 第四章 結果與討論…………………………………………40 4.1 金粒的尺寸與密度材料分析………………………………….40 -SEM -TEM -AFM 4.2 金奈米晶體記憶體元件電性量測…………………………….50 4.2.1 Al/SiO2/AuNCs/SiO2/p-Si 結構 (Run 9 ) ………………..50 4.2.1-1 寫入與抹除………………………………………...50 4.2.1-2 探討結果…………………………………………...51 4.2.2 Al/LaxO1-x(20 nm)/AuNCs/SiO2(7 nm)/p-Si 結構 (Run 10)……………………………………………………56 4.2.2.1 寫入與抹除………………………………………...56 4.2.2.2 retention…………………………………………….56 4.2.2.3 探討結果…………………………………………...57 4.2.2-1 Al/LaxO1-x(20 nm)/AuNCs/SiO2(7 nm)/p-Si 結構with RTA (Run 14)……………………………………………65 4.2.2-1.1 寫入與抹除………………………………………65 4.2.2-1.2 retention…………………………………………..65 4.2.2-1.3 探討結果…………………………………………65 4.2.2-2 Al/LaxO1-x(30 nm)/AuNCs/SiO2(5 nm)/p-Si 結構 (Run 12)…………………………………………………69 4.2.2-2.1 寫入與抹除………………………………………69 4.2.2-2.2 retention…………………………………………..69 4.2.2-2.3 探討結果…………………………………………69 4.2.2-3 Al/LaxO1-x(30 nm)/AuNCs/SiO2(5 nm)/p-Si 結構 with RTA(Run13)……………….……………………………74 4.2.2-3.1 寫入與抹除………………………………………74 4.2.2-3.2 retention…………………………………………..74 4.2.2-3.3 endurance……………………………………… ..74 4.2.2-3.4 探討結果…………………………………………74 4.2.2-4 Al/LaxO1-x(20 nm)/AuNCs/SiO2(5 nm)/p-Si 結構 with RTA (Run 15)……………………………………………80 4.2.2-4.1 寫入與抹除………………………………………80 4.2.2-4.2 retention…………………………………………..80 4.2.2-4.3 探討結果…………………………………………80 4.3 寫入與抹除分析……………………………………………….83 -I-V特性量測與解釋…………………………………..…....83 第五章 結論…………………………………………………89 附錄…………………………………………………………...91

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