隨著矽半導體在短通道製程中遇到越來越多瓶頸，由於二維半導體與生
俱來的物理特性以及奈米級的厚度，他的出現替半導體的下一個世代提供
了一個答案。在本論文當中使用多層的N 型二硫化鎢作為通道材料，主
要有兩種製備方式，第一種是藉由垂直堆疊單層二硫化鎢取得三層的材
料，並且以拉曼光譜和光致螢光量測取得材料層數相關訊息，第二種是藉
由塊材撕貼取得，其比起CVD 成長具有更加穩定的品質以及更少的缺陷，
材料製備完成後，我們分別在上下閘極使用5nm Al2O3+10nm HfO2 以及
300nm SiO2 作為氧化層，並且使用低功函數的鋁作為接觸金屬，就理論來
說其可以與N 型材料形成良好的接觸，並且降低蕭特基能障的高度，在我
們的實驗當中也會使用變溫量測的方法實際萃取出蕭特機能障的數值，確
認我們的接觸品質，最後，在完成雙閘極元件後，此結構主要的特性是可
以藉由給予其中一邊的閘極偏壓進而對通道中的載子濃度進行摻雜，同時
使用另一邊的閘極調控通道中的載子，藉由此種方式可以有效調控我們元
件的臨界電壓，以利未來在邏輯電路方面可以有更多的應用。

As silicon semiconductors face increasing bottlenecks in short-channel
processes, the inherent physical properties and nanometer-scale thickness of
two-dimensional (2D) semiconductors offer a solution for the next generation
of semiconductors. In this thesis, multi-layer N-type WS2 is used as
the channel material. There are two main preparation methods: the first involves
obtaining a three-layer material by vertically stacking single layers of
WS2, with Raman spectroscopy and photoluminescence measurements providing
information related to the number of layers. The second method involves
mechanical exfoliation from bulk material, which, compared to CVD
growth, yields more stable quality and fewer defects.

After preparing the material, we use 5nm Al2O3 + 10nm HfO2 and 300nm
SiO2 as the oxide layers for the top and bottom gates, respectively. Aluminum,
with its low work function, is used as the contact metal. Theoretically,
it forms good contact with the N-type material and reduces the
Schottky barrier height. In our experiments, we will also use temperaturedependent
measurements to extract the Schottky barrier values, confirming
the quality of our contacts.

Finally, upon completing the dual-gate device, the primary feature of this
structure is the ability to dope the carrier concentration in the channel by
applying a gate voltage on one side, while using the other gate to control
the carriers in the channel. This method allows for effective modulation of
the device’s threshold voltage, facilitating more applications in future logic
circuits.

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