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研究生: 林敬凱
Lin, Ching-Kai
論文名稱: A Hardware-Efficient FFT Processor for WMAN/WLAN/UWB Applications
應用於無線都會/區域網路/超寬頻具硬體效益的快速傅立葉轉換處理器
指導教授: 張慶元
Chang, Tsin-Yuan
口試委員: 陳竹一
洪進華
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2011
畢業學年度: 100
語文別: 中文
論文頁數: 82
中文關鍵詞: 快速傅立葉轉換處理器無線都會網路無線區域網路超寬頻記憶體式
外文關鍵詞: Fast Fourier Transformprocessor, WMAN, WLAN, UWB, memory-based
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  • 此論文中,提出了一個可變點數運算且具硬體效益的快速傅立葉轉換(FFT)處理器,應用於可調變多輸入多輸出(MIMO)的正交分頻多工存取(OFDM),尤其適合無線都會網路(WMAN)、無線區域網路(WLAN)、超寬頻(UWB),而正交分頻多工存取是一個近來運用於無線通訊系統實體層(PHY)的核心技術。針對這三種無線網路系統,IEEE工作小組發表了相關的標準包括802.16e(因應WMAN),802.11n(因應WLAN),802.15.3a(因應UWB)。在研究裡,我們使用了管線式(pipeline)的多路徑延遲回授(MDF)在記憶體式(memory-based)架構的主軸上,來提升整體的產出率(throughput rate)。為了提升訊號對雜訊量子化比率(SQNR),區塊調整(block scaling)及多資料調整(multi-data scaling)方法被我們應用在所提出的快速傅立葉轉換處理器上。而藉由使用分離式快取記憶體(interleave cache)來減少主要記憶體的存取次數以及分享計算元件,可以降低面積及功率消耗的硬體成本。最後,伴隨著我們給多路徑運算的記憶體最佳化存取設計,單埠靜態隨機存取記憶體(single-port SRAM)被使用在我們的設計中。而此測試晶片是採用TSMC 0.18-μm 1P6M CMOS製程所設計,面積為4.77平方公厘。在無線都會網路應用,需要52.6微秒處理操作在20MHz四條路徑的2048點快速傅立葉轉換運算,功率消耗是40.97毫瓦,而訊號對雜訊量子化比率超過48分貝。在無線區域網路應用時,功率消耗是59.6毫瓦操作在40MHz四條路徑的128點快速傅立葉轉換運算;而在超寬頻的104MHz單路徑128點快速傅立葉轉換運算下,功率消耗僅需要123.5毫瓦。


    In this thesis, the hardware-efficient Fast Fourier Transform (FFT) processor with flexible point-lengths is proposed to penetrate into applications of variable MIMO-OFDM (Orthogonal Frequency Division Multiplexing) system, one of the principle technologies in recent wireless communications, and is demonstrated especially suitable for the WMAN/WLAN/UWB. The databases are specified for WMAN/WLAN/UWB systems, defined by IEEE 802.16e/802.11n/802.15.3a standards which were based on IEEE work group, respectively. This study employed the multi-path delay feedback (MDF) of pipeline architecture into memory-based FFT processor to raise its throughput-rate (T.R.). In order to achieve SQNR requirements, the block scaling and multi-data scaling methods were used in the proposed FFT kernel. In behalf of reducing hardware cost, the interleave caches were utilized for decreasing memory access times and sharing calculating units. Finally, the single-port SRAM was introduced into the presented architecture with optimized memory-access scheme for multi-path processing. The test chip has been successfully designed and fabricated by using TSMC 0.18-μm 1P6M CMOS process with the core area 4.77 mm2. In WMAN, the proposed processor has demonstrated to perform four-stream 2048-point FFT within 52.6 μs at working frequency of 20MHz; moreover, the power dissipation is 40.97 mW, and the SQNR performance is above 48 dB. It is also showed that the power consumption is only 59.6 mW at working clock rate of 40MHz for WLAN by operating four-stream 128-point FFT, and is no more than 123.5 mW at clock rate of 104MHz for UWB by operating one-stream 128-point FFT.

    誌謝 III 中文摘要 IV ABSTRACT V CONTENTS VI LIST OF FIGURES VIII LIST OF TABLES X CHAPTER 1 INTRODUCTION 1 1.1 INTRODUCTION 1 1.2 PREVIOUS WORK 4 1.3 MOTIVATION 6 1.4 THESIS ORGANIZATION 7 CHAPTER 2 FFT/IFFT ALGORITHM 8 2.1 2048-POINT FFT ALGORITHM 8 2.1.1 Decomposition of 64-point Inner DFT 12 2.1.2 Decomposition of 32-point Outer DFT 15 2.2 128-POINT FFT ALGORITHM 17 2.3 INVERSE FAST FOURIER TRANSFORM ALGORITHM 19 2.4 SUMMARIZATION 19 CHAPTER 3 PROPOSED FFT PROCESSOR 21 3.1 THE PROPOSED ARCHITECTURE 21 3.2 PROPOSED USAGE OF MEMORY SCHEME 25 3.2.1 The Overview of Main Memory 25 3.2.2 Considerations of Memory Design 26 3.2.3 Memory Access for WMAN 30 3.2.4 Memory Access for WLAN and UWB 39 3.3 PROPOSED MULTIMODE FFT KERNEL 41 3.3.1 Previous Work 41 3.3.2 Architecture of Processing Element 44 3.3.3 Multi-Data Scaling 49 3.3.4 The Simplified Scheme of Multiplication 51 3.3.5 Operation Mode for WMAN 61 3.3.6 Operation Mode for WLAN 67 3.4 SUMMARIZATION 69 CHAPTER 4 IMPLEMENTATION RESULTS 71 4.1 IMPLEMENTATION RESULT 71 4.2 COMPARISON 73 CHAPTER 5 CONCLUSIONS 77 5.1 CONCLUSIONS 77 5.2 FUTURE WORK 78 REFERENCE 79

    [1] Y. H. Yuan, “Design and Implementation of a High performance Closed-Loop MIMO Communications with Ultra Low Complexity Handset,” M.S. thesis, Dept. Electrical Engineering, National Tsing-Hua University, Hsinchu, Taiwan, 2010.
    [2] [Online].Available: http://www.ieee802.org/misc-docs/GlobeCom2009/GlobeCom2009.shtml
    [3] [Online].Available: http://ieee802.org/16/tge/
    [4] [Online].Available: http://www.ieee802.org/11/index.shtml
    [5] [Online].Available: http://www.ieee802.org/15/pub/TG3a.html
    [6] H. Ishebabi, G. Ascheid, H. Meyr, O. Atak, A. Atalar, E. Arikan, “An Efficient Parallelization Technique for High Throughput FFT-ASIPs,” IEEE International Symposium on Circuits and Systems, pp. 21-24, 2006.
    [7] S. He and M. Torkelson, “Designing pipeline FFT processor for OFDM (de)modulation,” in Proc. URSI Int. Symp. Signals, Systems, and Electronics, vol. 29, pp. 257-262, Oct. 1998.
    [8] J. Y. Oh and M. S. Lim, “Area and Power Efficient Pipeline FFT Algorithm,” IEEE Workshop on Signal Processing Systems Design and Implementation, pp. 520-525, 2005.
    [9] Y. W. Lin, H. Y. Liu, and C. Y. Lee, “A 1-GS/s FFT/IFFT processor for UWB applications,” IEEE Journal of Solid-State Circuits, vol. 40, pp. 1726-1735, 2005.
    [10] L. Liu, J. Y. Ren, X. J. Wang, and F. Ye, “Design of Low-Power, 1GS/s Throughput FFT Processor for MIMO-OFDM UWB Communication System,” IEEE International Symposium on Circuits and Systems, pp. 2594-2597, 2007.
    [11] M. Shin and H. H. Lee, “A high-speed four-parallel radix-24 FFT/IFFT processor for UWB applications,” IEEE International Symposium on Circuits and Systems, pp. 960-963, 2008.
    [12] L. G. Johnson, “Conflict free memory addressing for dedicated FFT hardware,” IEEE Transactions on Circuits and Systems II, vol. 39, pp. 312-316, 1992.
    [13] D. Veithen, P. Spruyt, T. Pollet, M. Peeters, S. Braet, O. Van de Wiel, and H. Van De Weghe, “A 70 Mb/s variable-rate DMT-based modem for VDSL,” IEEE International Solid-State Circuits Conference, pp. 248-249, 1999.
    [14] R. Radhouane, P. Liu, and C. Modlin, “Minimizing the memory requirement for continuous flow FFT implementation: continuous flow mixed mode FFT (CFMM-FFT),” IEEE International Symposium on Circuits and Systems, vol. 1, pp. 116-119 vol.1, 2000.
    [15] B. G. Jo and M. H. Sunwoo, “New continuous-flow mixed-radix (CFMR) FFT Processor using novel in-place strategy,” IEEE Transactions on Circuits and Systems I, vol. 52, pp. 911-919, 2005.
    [16] B. M. Baas, “A low-power high-performance 1024-point FFT processor,” IEEE Journal of Solid-State Circuits, vol. 34, pp. 380-387, 1999.
    [17] J. C. Kuo, C. H.Wen, C. H. Lin, and A. Y.Wu, “VLSI design of a variable-length FFT/IFFT processor for OFDM-based communication systems,” EURASIP J. Appl. Signal Process., vol. 2003, no. 13, pp. 1306–1316, Dec. 2003.
    [18] T. H. Yu, C. Z. Zhan, Y. J. Cho, C. L. Yu, and A. Y. Wu, “Efficient fast Fourier transform processor design for DVB-H system,” in Proc. 18th VLSI/CAD Symp., pp. 65–68, Aug. 2007.
    [19] C. L. Hung, S. S. Long, and M. T. Shiue, “A low power and variable-length FFT processor design for flexible MIMO OFDM systems,” IEEE International Symposium on Circuits and Systems, pp. 705-708, 2009.
    [20] J. J. Cheng, “A High Efficient FFT Processor for WiMAX/WLAN,” M.S. thesis, Dept. Electrical Engineering, National Tsing-Hua University, Hsinchu, Taiwan, 2010.
    [21] S. N. Tang, J. W. Tsai, and T. Y. Chang, “A 2.4-GS/s FFT Processor for OFDM-Based WPAN Applications,” IEEE Transactions on Circuits and Systems II, vol. 57, pp. 451-455, 2010.
    [22] Y. W. Lin, H. Y. Liu, and C. Y. Lee, “dynamic scaling FFT processor for DVB-T applications,” IEEE Journal of Solid-State Circuits, vol. 39, pp. 2005-2013, 2004.
    [23] Y. Chen, Y. W. Lin, and C. Y. Lee, “A Block Scaling FFT/IFFT Processor for WiMAX Applications,” IEEE Asian Solid-State Circuits Conference, pp. 203-206, 2006.
    [24] Y. Chen, Y. C. Tsao, Y. W. Lin, C. H. Lin, and C. Y. Lee, “An Indexed-Scaling Pipelined FFT Processor for OFDM-Based WPAN Applications,” IEEE Transactions on Circuits and Systems II, vol. 55, pp. 146-150, 2008.
    [25] A. V. Oppenheim, R. W. Schafer, and J. R. Buck, “Computation of the discrete Fourier Transform,” in Discrete-Time Signal Processing, 2nd ed. New Jersey: Prentice-Hall, ch. 9, sec. 1, pp. 630-633, 1999.
    [26] H. Y. Lee and I. C. Park, “Balanced Binary-Tree Decomposition for Area-Efficient Pipelined FFT Processing,” IEEE Transactions on Circuits and Systems I, vol. 54, pp. 889-900, 2007.
    [27] S. M. Kim, J. G. Chung, and K. K. Parhi, “Low error fixed-width CSD multiplier with efficient sign extension,” IEEE Transactions on Circuits and Systems II, vol. 50, pp. 984-993, 2003.
    [28] “CIC Referenced Flow for Cell-based IC Design”, Technical Report, CIC-DSD-RD-08-01, V1.0, National Chip Implementation Center, Hsinchu, Taiwan, May, 2008.
    [29] C. H. Liao, “A High-Throughput-Rate FFT Processor for OFDM Based WPAN/WLAN Applications,” M.S. thesis, Dept. Electrical Engineering, National Tsing-Hua University, Hsinchu, Taiwan, 2010.

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