隨著新世代的互補式金屬氧化物半導體縮小至奈米等級，我們必須使用更高解析度的黃光製程和更精密的儀器來製作高密集度的晶片。同時，金屬接線和多晶矽線也會為了符合電晶體的奈米等級而越來越細窄，這將會使片電阻的值變的相當大而帶來相當大的寄生電阻。為了探討多晶矽上的寄生電阻的影響，我們使用分散式電阻的模型來建構模擬電路，並觀察對電路延遲和耗能的影響。基於分散式電組的模型，我們開發出一個新的方法去估算應該將多晶矽線切成多少段可以獲得高準確的模擬結果。之後我們專注在當閘極電阻增加時，其如何影響電路的效能。考量到鰭式電晶體的電路布局方法，P型和N型的多晶矽線之電阻率將是影響傳輸延遲的一個重要因素，我們觀察電阻率改變時之趨勢以獲得結果如下：當P型和N型多晶矽的電阻率相同時，將可以消除傳輸延遲的差距，並減少短路電流所造成的能量浪費以增進電路效能。

As the size of new generation CMOS technology developed to nano-meter level, we need to use higher resolution lithography and more delicate process to deal the high density chip layout. The interconnect and polyline become more narrow to match with nano-level transistor, which will brings large parasitic resistance due to the sheet resistance becomes much larger. To study the influence of parasitic poly resistance, we use the distributed resistance model to build a simulation circuit, and observe the impacts on delay and energy performance. Based on distributed resistance model, we develop a methodology to estimate how many segments the polyline should be cut for high accurate simulations. After that, we focus on the detail about what will change and how does gate resistance affect circuit performance when it is increasing. Consider the FinFET layout, the resistivity of PN polyline will be an important factor to influence the propagation delay on the two polyline. We observe the tendency when resistivity changing, and derive a result: we should let the resistivity of P-poly and N-poly same. It can eliminate the different of propagation delay on P-gate and N-gate, and reduces the energy wasting by short circuit current, improves the circuit performance.

Reference
[1] Gordon E. Moore, “Cramming More Components onto Integrated Circuits,” Electronics, volume 38, number 8, April 19, pp.114-117, 1965.
[2] Ning Lu, Terence B. Hook, Jeffrey B. Johnson, Carl Wermer, Christopher Putnam, and Richard A. Wachnik,“Efficient and Accurate Schematic Transistor Model of FinFET Parasitic Elements,” IEEE Electron Device Letters, vol. 34, no. 9, Sept. 2013.
[3] Edgar Solis Avila, Julio C. Tinoco, Senior Member, IEEE, Andrea G. Martinez-Lopez, Mario Alfredo Reyes-Barranca, Antonio Cerdeira, and Jean-Pierre Raskin, Fellow, “Parasitic Gate Resistance Impact on Triple-Gate FinFET CMOS Inverter,” IEEE Transactions on Electron Devices, vol. 63, no. 7, pp. 2635 – 2642, July 2016.
[4] Ning Lu, Terence B. Hook, Jeffrey B. Johnson, Carl Wermer, Christopher Putnam, and Richard A. Wachnik,“Efficient and Accurate Schematic Transistor Model of FinFET Parasitic Elements,” IEEE Electron Device Letters, vol. 34, no. 9, Sept. 2013.

[5] Synopsys. (2008), HSPICE User Guide: Simulation and Analysis, Synopsys, 2008
[6] Ashis Kumar Mal, Anindya Sundar Dhar, “Modified Elmore Delay Model for VLSI Interconnect,” Circuits and Systems (MWSCAS), 2010.
[7] Akio Hirata, Hidetoshi Onodera, and Keikichi Tamaru, “Estimation of Propagation Delay Considering Short-Circuit Current for Static CMOS Gates,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 45, no.11, Nov 1998.
[8] Kenichi Miyaguchi , “Modeling FinFET Metal Gate Stack Resistance for 14nm Node and Beyond,” IC Design & Technology (ICICDT), International Conference on, 2015
[9] G.-L. Chen, “Exploring FinFET Cell Layout to Minimize Parasitic Impacts,” master thesis, NTHU, July 2016
[10] H.-Y. Lin, “Parasitic Impacts on Sub-20nm FinFET Transistors,” master thesis, NTHU, July 2016