隨著更高的資料傳輸速度與更好的服務需求的增加，先進的無線通訊系統開始採用更有效且更先進的數位調變方式。然而，為了達到這個目的，射頻傳收機的設計趨向於越來越困難。為了不單在類比電路設計上改上電路性能，我們提出幾個數位校正補償的方法來改善類比電路的不完美現象，並且因著數位補償電路與類比電路相互合作的關係來進一步改善整體射頻傳收機的效能。
最近幾年，以數位訊號處理技術來補償傳收機中I/Q不平衡現象的演算法持續被提出來。但是在這些演算法都存在著共同的缺點：1) 需要額外硬體來收集回饋資訊，2) 在發射端的I/Q不平衡現象常被假設忽略，3) 在回饋電路中所造成的失真會造成演算法中不可回覆的誤差，4) 需要額外訓練用的參考訊號。在本論文的第二章中，我們提出一個可以同時補償發射端與接收端I/Q不平衡的問題，並且可以解決前面所提出來的問題。
採用數位預先失真來提升功率放大器線性度已經被證明是一個有效的方法，但是在傳統預先失真器中面臨兩個問題：1) 對於查表法的預先失真器而言，為了達到功率放大器的非線性補償，演算法收斂時間很長，2) 對於多項式預先失真器而言，為了達到功率放大器的非線性補償，演算法的電路複雜度會很高。所以在本論文第三章中，我們提出一個透過低階多項式預先失真器與小面積查表預先失真器彼此間合作來達到能有效改善功率放大器非線性失真的目的，並且可以解決前面所提的問題。
高速高解析度的數位類比轉換器在無線通訊系統中是相當重要的一個元件。在第四章中我們提出一個數位校正的機制來改善高解析度數位類比轉換器的線性度。這個數位類比轉換器可以達到14位元的解析度，並且透過背景校正機制來改善線性度的同時並保有原本高速操作的特性。實驗結果證明，經過數位補償校正之後INL/DNL可以小於0.55 LSB. 在150 MS/s的取樣速度下，對於1.6 MHz的輸入訊號而言可以達到81 dB的SFDR，對於48.75 MHz的輸入訊號而言可以達到67 dB的SFDR。整個數位類比轉換器是在0.35μm的CMOS製成下設計完成，面積為2.4x1.1 mm2。

With increasing demands for higher data rate and better services, more efficient and advanced modem techniques are being adopted by many wireless standards. However, to achieve this goal, the design of RF transceiver towards more and more critical. Instead of doing the RF transceiver design in pure analog way, we propose several digital calibration techniques to cooperate with the analog RF transceiver and these digital compensation techniques help to correct for the analog imperfections which in turn improve the overall RF transceiver performance.

Several digital signal processing-assisted (DSP-assisted) error compensation techniques are reported in recent years to solve the in-phase/quadrature (I/Q) imbalance problem in a quadrature transceiver and achieve outstanding performance because of their high precision in system control and their excellent °exibility in circuit adaptation. However, some common drawbacks exist in these DSP-assisted techniques: 1) extra hardware cost is required on collecting feedback information for DSP, 2) the I/Q imbalance of the remote transmitter is impractically assumed to be perfectly tuned, 3) signal distortion introduced in the feedback link for DSP is irreversible, and 4) additional on-line DSP training is required. In chapter 2 of this dissertation, we propose a novel DSP-assisted scheme to compensate the I/Q imbalance jointly for the transmitter and the receiver, and at the same time to eliminate the drawbacks mentioned above. The advantages of the proposed scheme, in terms of its high accuracy, low complexity, and suitable for practical applications, will be demonstrated through analyses and extensive computer simulations. Digital predistortion at baseband is an effcient and low-cost method for the linearization of a power amplifier (PA) in a wireless system employing a non-constant- envelop modulation scheme, so as to reduce the adjacent channel interference. The polynomial and the look-up table (LUT) predistortion schemes are two commonly-used approaches. However, in each of both approaches, to reach an satisfactory adjacent channel power ratio (ACPR) in the PA output signal, people usually ends up with a complex system having the involved algorithms converge rather slowly. In the chapter 3 of this dissertation, we propose a low-complexity joint-polynomial-and-LUT predistortion PA linearizer, where the two mutually-dependent predistortion schemes can skillfully help each other. Simulation results show that the proposed joint linearizer can reduce the algorithm convergence time while achieving an excellent ACPR.

Digital-to-analog converters (DACs) are essential components in communication system and are inherent nonlinear when high resolution DAC is designed. Chapter 4 of this dissertation presents a digital background self calibration technique for high- resolution current-steering CMOS DACs. The DAC core uses a true background self- calibration technique to obtain 14-b accuracy while simple analog current cell design is retained. The proposed digital background calibration technique can resolve the inherent drawbacks in the popular calibration schemes and make the calibration scheme more applicable to practical implementation. The DAC with background calibration loop trims the static performance to less than 0.55 LSB. The DAC achieves maximum spurious free dynamic range (SFDR) of 81 dB for an input frequency of 1.6 MHz and 67 dB for an input frequency of 48.75 MHz at a sampling rate of 150 MS/s. The DAC is implemented
in a 0.35 ¹m CMOS process and occupies active area of 2.4 x 1.1 mm2. At 150 MS/s power consumption is 165 mW from a 3.3-V power supply.

[1] A. Bateman and D. M. Haines, \Direct conversion transceiver design for compact low-cost portable
mobile radio terminals," IEEE Vehicular Technology Conference, vol. 1, pp. 57-62, May. 1989.
[2] A. A. Abidi, \Direct-conversion radio transceivers for digital communications ," IEEE Journal of
Solid-State Circuits, vol. 30, pp. 1399-1410, Dec. 1995.
[3] B. Razavi, \Design Considerations for Direct-Conversion Receivers," IEEE Transactions on Circuits
and Systems-II, vol. 44, pp. 428-435, Jun. 1997.
[4] J. Crols and M. S. J. Steyaert, \Low-IF topologies for high-performance analog front ends of fully
integrated receivers ," IEEE Transactions on Circuits and Systems-II, vol. 45, pp. 269-282, Mar.
1999.
[5] J. Crols and M. S. J. Steyaert, \A single-chip 900 MHz CMOS receiver front-end with a high
performance low-IF topology ," IEEE Journal of Solid-State Circuits, pp. 1483 -1492, Dec. 1995.
[6] J. Sevenhans, D. Haspeslagh, A. Delarbre, L. Kiss, Z. Chang, and J. F. Kukielka, \An analog radio
front-end chip set for a 1.9 GHz mobile radio telephone application ," IEEE Solid-State Circuits
Conference, pp. 16-18, Feb. 1994.
[7] M. Faulkner, M. Johansson, and W. Yates, \Automatic adjustment of quadrature modulators,"
Electronics Letters , vol. 27, pp. 214-216, Jan. 1991.
[8] J. K. Cavers and M. W. Liao, \Adaptive compensation for imbalance and o®set losses in direct
conversion transceivers," IEEE Transactions on Vechicular Technology, vol. 42, pp. 581-588, Nov.
1993.
[9] L. Yu and W. M. Snelgrove, \A novel adaptive mismatch cancellation system for quadrature IF
radio receivers," IEEE Transactions on Circuits and Systems-II, vol. 46, pp. 789-801, Jun. 1999.
[10] M. Valkama, M. Renfors, and V. Koivunen, \Advanced methods for I/Q imbalance compensation
in communication receivers," IEEE Transactions on Signal Processing, vol. 49, pp. 2335-2344, Oct.
2001.
[11] C. C. Chen and C. C. Huang, \On the architecture and performance of a hybrid image rejection
receiver," IEEE Journal on Selected Areas in Communications, vol. 19, pp. 1029-1040, June. 2001.
80
81
[12] I. H. Sohn, E. R. Jeong, and Y. H. Lee, \Data-Aided Approach to I/Q Mismatch and DC O®set
Compensation in Communication Receivers," IEEE Communications Letters, vol. 6, pp. 547-549,
Dec. 2002.
[13] J. P. F. Glas, \Digital I/Q imbalance compensation in a low-IF receiver," IEEE Global Telecom-
munications Conference, vol. 3, pp. 8-12, Nov. 1998.
[14] I. Vassiliou, K. Vavelidis, T. Georgantas, S. Plevridis, N. Haralabidis, G. Kamoulakos, C. Kapnistis,
S. Kavadias, Y. Kokolakis, P. Merakos, J.C. Rudell, A. Yamanaka, and S. Bouras, I. Bouras,
\A single-chip digitally calibrated 5.15-5.825-GHz 0.18-¹m CMOS transceiver for 802.11a wireless
LAN," IEEE Journal of Solid-State Circuits, vol. 38, pp. 2221-2231, Dec. 2003.
[15] G. Xing, M. Shen, and H. Liu, \Frequency o®set and I/Q imbalance compensation for OFDM direct-
conversion receivers ," IEEE International Conference on Acoustics, Speech, and Signal Processing,
vol. 4, pp. 6-10, April. 2003.
[16] J. K. Cavers, \Ampli‾er linearization using a digital predistorter with fast adaptation and low
memory requirements," IEEE Transactions on Vechicular Technology, vol. 39, pp. 374-382, Nov.
1990.
[17] H. H. Chen, C. S. Maa, Y. C. Wang, and J. T. Chen, \Joint polynomial and look-up-table power
ampli‾er linearization scheme," IEEE Vehicular Technology Conference, vol. 2, pp. 1345 -1349, Apr.
2003.
[18] J. K. Cavers, \The e®ect of quadrature modulator and demodulator errors on adaptive digital
predistorters for ampli‾er linearization," IEEE Transactions on Vechicular Technology, vol. 46, pp.
456-466, May. 1997.
[19] Y. Nagata, \Linear ampli‾cation technique for digital mobile communications ," IEEE Vehicular
Technology Conference, vol. 1, pp. 159-164, May. 1989.
[20] A. A. Saleh , \Frequency-independent and frequency-dependent nonlinear models of TWT ampli‾ers
," in IEEE Transaction on Communications , vol. COM-29,no. 11, pp. 1715-1720, Nob. 1981.
[21] S. Haykin, \Adaptive Filter Theory, Third Edition," Prentice Hall, 1996.
[22] Wireless LANMAC and PHY Speci‾cations: High-Speed Physical Layer in the 5 GHz Band, IEEE
Standard 802.11a-1999, 2000.
[23] "UE Radio Transmission and Reception (FDD)," Third-Generation Partnership Project (3GPP),
Tech. Spec. 25.101, v. 3.0.1, Apr. 2000.
82
[24] S. P. Stapleton, G. S. Kandola, and J. K. Cavers, \Simulation and analysis of an adaptive pre-
distorter utilizing a complex spectral convolution ," IEEE Transactions on Vechicular Technology,
vol. 41, pp. 387-394, Nov. 1992.
[25] H. Besbes, T. Le-Ngoc, and H. Lin, \A fast adaptive polynomial predistorter for power ampli‾ers
," Global Telecommunications Conference, vol. 1, pp. 659-663 , Jul. 2001.
[26] Y. Nagata, \Linear ampli‾cation technique for digital mobile communications," IEEE Vehicular
Technology Conference, vol. 1, pp. 159-164, 1989.
[27] A. S. Wright, and W.G. Durtler, \Experimental performance of an adaptive digital linearized power
ampli‾er ," IEEE Transactions on Vechicular Technology, vol. 41, pp. 395-400, Nov. 1992.
[28] M. Faulkner, and M. Johansson, \Adaptive linearization using predistortion-experimental results
," IEEE Transactions on Vechicular Technology, vol. 43, pp. 323-332, May. 1994.
[29] L. Sundstrom, M. Faulkner, and M. Johansson, \Quantization analysis and design of a digital
predistortion linearizer for RF power ampli‾ers ," IEEE Transactions on Vechicular Technology,
vol. 45, pp. 707-719, Nov. 1996.
[30] J. K. Cavers, \Optimum table spacing in predistorting ampli‾er linearizers," IEEE Transactions
on Vechicular Technology, vol. 48, pp. 1699-1705, Sep. 1999.
[31] K. J. Muhonen, M. Kavehrad, and R. Krishnamoorthy, \Look-up table technique for adaptive digital
predistortion: a development and comparison ," IEEE Transactions on Vechicular Technology, vol.
49, pp. 1995-2002, Sep. 2000.
[32] S. Kusunoki, K. Yamamoto, T. Hatsugai, H. Nagaoka, K. Tagami, N. Tominaga, K. Osawa, K.
Tanabe, S. Sakurai, and T. Iida, \Power-ampli‾er module with digital adaptive predistortion for
cellular phones ," in IEEE Transactions on Microwave Theory and Techniques, vol. 50 ,pp. 2979-
2986, Dec. 2002.
[33] T. Matsuoka, M. Orihashi, M. Sagawa, H. Ikeda, and K. Misaizu, \Compensation of nonlinear
distortion during transmission based on the adaptive predistortion method ," in IEICE Transactions
on Electron, vol. E80-C ,pp. 782 -787, Jun. 1997.
[34] S. Takabayashi, M. Orihashi, T. Matsuoka, and M. Sagawa, \Adaptive predistortion linearizer with
digital quadrature modem," in IEEE Vehicular Technology Conference, vol. 3,pp. 2237 -2241, 2000.
[35] A. A. Saleh , \Frequency-independent and frequency-dependent nonlinear models of TWT ampli‾ers
," in IEEE Transaction on Communications , vol. COM-29,no. 11, pp. 1715-1720, Nob. 1981.
83
[36] J.-T. Chen, H.-S. Tsai, and Y.-K. Chen, \The Optimal RLS Parameter Tracking Algorithm for
a Power Ampli‾er Feed-Forward Linearizer ," in IEEE Transaction on Circuits and Systems II:.
Analog and Digital Signal Processing , vol. 46, pp. 464 -468, Apr. 1999.
[37] S. Haykin, \Adaptive Filter Theory, Third Edition ," Prentice Hall, 1996.
[38] H.-H. Chen, and J.-T. Chen, \Joint Polynomial and Look-Up-Table Power Ampli‾er Linearization
Scheme," IEEE Vehicular Technology Conference,, Apr. 2003.
[39] B. Holdsworth, and C. Woods, \Digital Logic Design, Fourth Edition" Newnes, 2002.
[40] S. Smith, \Microelectronic Circuits, Third Edition" Saunders College Publishing, 1991.
[41] P. Hendriks, \Specifying communication DAC's," IEEE Spectrum, pp. 58-69, Jul. 1997.
[42] I. Mehr, M. Prabir, and D. Paterson,\ A 12-bit integrated analog front end for broadband wireline
networks," IEEE Journal of Solid-State Circuits, vol. 37, pp. 302-309, May 2001.
[43] M. Pelgrom, A. Duinmaijer, A. Welbers,\Matching properties of MOS transistors," IEEE Journal
of Solid-State Circuits, vol. 24, pp. 1433-1440, Oct. 1989.
[44] M. Borremans, V. Bosch, M. Steyaert, and W. Sansen, "A low power, 10-b CMOS D/A converter
for high speed applications," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), May 2001,
pp. 157-160.
[45] C.-H. Lin and K. Bult, "A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2," " IEEE Journal of
Solid-State Circuits, vol. 33, pp. 1948-1958, Dec. 1998.
[46] J. Bastos, A. Marques, M. Steyaert and W. Sansen, "A 12-b intrinsic accuracy high-speed CMOS
DAC," " IEEE Journal of Solid-State Circuits, vol. 33, pp. 1959-1969, Dec. 1998.
[47] G. A. M. V. D. Plas, J. Vandenbussche, W. Sansen, M.S.J. Steyaert, G.G.E Gielen, "A 14-b
intrinsic accuracy Q2 random walk CMOS DAC" " IEEE Journal of Solid-State Circuits, vol. 34,
pp. 1708-1718, Dec. 1999.
[48] K. O'Sullivan, C. Gorman, M. Hennessy, and V. Callaghan, "A 12-bit 320-MSample/s current-
steering CMOS D/A converter in 0.44 mm2," " IEEE Journal of Solid-State Circuits, vol. 39, pp.
1064-1072, Jul. 2004.
[49] J. Deveugele, and M. S. J. Steyaert, "A 10-bit 250-MS/s binary-weighted current-steering DAC,"
" IEEE Journal of Solid-State Circuits, vol. 41, pp. 320-329, Feb. 2006.
84
[50] D. W. J. Groenveld et al., "A self-calibration technique for monolithic high-resolution D/A con-
verters," " IEEE Journal of Solid-State Circuits, vol. 24, pp. 1517-1522, Dec. 1989.
[51] A. Bugeja and B.-S. Song, "A self-trimming 14-b 100-MS/s CMOS DAC," " IEEE Journal of
Solid-State Circuits, vol. 35, pp. 1841-1852, Dec. 2000.
[52] Y. Cong and R. L. Geiger, "A 1.5V 14-b 100-MS/s self-calibrated DAC ," " IEEE Journal of
Solid-State Circuits, vol. 38, pp. 2051-2060, Dec. 2003.
[53] D. Mercer, "A study of error sources in current steering digital-to-analog converters," in Proc. "
IEEE Custom Integrated Circuits Conf. (CICC), Oct. 2004, pp. 185-190.
[54] T.-H. Shu, B.-S. Song, and K. Bacrania, "A 13-b 10-Msample/s ADC Digitally Calibrated with
Oversampling Delta-Sigma Converter," " IEEE Journal of Solid-State Circuits, vol. 30, pp. 443-
452, Apr. 1995.
[55] A. Van den Bosch, M. Steyaert, and W. Sansen, "An accurate statistical yield model for CMOS
current-steering D/A converters," in " IEEE Int. Symp. Circuits and Systems (ISCAS), May 2000,
pp. 105-108.
[56] B. Razavi, "Principles of data conversion system design", Piscataway, NJ: IEEE Press, 1995.
[57] K. Falakshahi, C-K K. Yang, and B. A. Wooley, "A 14-bit, 10-Msamples/s D/A converter using
multibit modulator ," " IEEE Journal of Solid-State Circuits, vol. 34, pp. 607-615, May. 1999
[58] Q. Huang, P. A. Francese, C. Matelli, J. Nielsen, "A 200MS/s 14b 97mW DAC in 0.18um CMOS
," in " IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2004, pp. 364-365.