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研究生： 黃培綸
Huang, Pei-Lung
論文名稱： 一個使用QEMU模擬的多核異質模擬環境
An embedded heterogeneous multicore emulation environment using QEMU
指導教授： 金仲達
KING, CHUNG-TA
口試委員: 呂仁碩
LIU, REN-SHUO
周百祥
CHOU, PAI-HSIANG
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年： 2020
畢業學年度： 108
語文別： 英文
論文頁數： 25
中文關鍵詞： 模擬 、嵌入式系統 、異質多核
外文關鍵詞： heterogeneous multicore
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    • 邊緣運算的特徵為運算單元與處存裝置非常的接近。近期這是一
    種趨勢去開發這種特徵的異質多核平台，如近期興起的由 NVDIA 所提
    供的 NVDLA 架構。這個架構是一個異質多核平台並嘗試找尋人工智慧
    推論、多媒體等應用在這個平台的所能表現的效能。進而找到不同的
    應用所對應的最佳硬體配置或是軟體解法。
    此篇論文提出使用 QEMU 來模擬的非對稱異質多核架構。其中這個
    架構包含 CPU 和 micro-controller。這個架構在於 micro-controller
    可以進行加速器的排程和接收加速器的中斷，進而分擔主 CPU 的負擔。
    然而目前單個 QEMU 的模擬只提供多核對稱式的架構，我們提出兩個
    QEMU 分別模擬 CPU 和 micro-controller。總結來說，此篇的貢獻為下
    列兩點: 探討 QEMU 觸發中斷的機制與設計兩個 QEMU 之間溝通的架構
    設計。

    The edge computing is characterized by bring computation and data storage closer
    to the location where it is need. With related edge computing architecture design
    being emerge such as NVDLA, it becomes a trend for new method to perform their
    architectural emulation. This emulation platform is a heterogeneous multi-cores
    platform to explore how the performance of application from intelligence inference,
    to multimedia human interface. Different application is suitable for different hardware support or software solution.
    This thesis presents a asymmetric heterogeneous multi-cores using two QEMU for
    simulating architecture consisting of CPU and micro-controller, which offloads accelerator scheduling, interrupt handling from CPU. Currently, QEMU only supports
    symmetric multi-cores emulation such as symmetric multi-processors or non-Uniform
    memory access. Our works emulate CPU and micro-controller by using two QEMU.
    It turns out that our work can be summarized into two main points. Firstly, we
    explore and discuss interrupt mechanism in QEMU. Secondly, we give a direction
    for different architecture design for different context application.

    Chinese Abstract i Abstract ii Acknowledgements iii Contents iv List of Figures vi List of Tables 1 1 Introduction 2 2 Background 4 2.1 QEMU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1.1 Operating mechanism in QEMU: dynamic binary translation . 5 2.1.2 Operating mechanism in QEMU: helper function . . . . . . . 5 2.1.3 How qemu emulate interrupt . . . . . . . . . . . . . . . . . . . 6 2.2 NVDLA project: large model . . . . . . . . . . . . . . . . . . . . . . 6 2.3 TMS320VC547x heterogeneous architecture . . . . . . . . . . . . . . 7 2.4 Full System Emulation of Embedded Heterogeneous multicores Based on QEMU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 System design 9 3.1 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 iv 3.2 Emulation flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 Initializing the microcontroller emulator and interfacing QEMU with microcontroller emulator . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 Interact with API device . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5 API device Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6 ARM sends event to MCU . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7 MCU fields the event and sends event back to ARM . . . . . . . . . . 15 3.8 ARM fields the event . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 Experiment 17 4.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3.1 Emulation Time . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3.2 Effects of Data Size . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3.3 Interrupt Reaction Time . . . . . . . . . . . . . . . . . . . . . 21 5 Conclusion 23

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