使用多層次回溯之低功率菲特比解碼器設計｜國立清華大學博碩士論文庫

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研究生：	方勇勝 Yung-Sheng Fang
論文名稱：	使用多層次回溯之低功率菲特比解碼器設計 Design of a Low-Power Viterbi Decoder with Multi-Stepping Traceback
指導教授：	黃錫瑜 Shi-Yu Huang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2005
畢業學年度：	93
語文別：	英文
論文頁數：	56
中文關鍵詞：	迴旋編碼器、菲特比解碼器、低功率、最少轉換回溯、高基底加法比較選擇單元
外文關鍵詞：	convolutional encoder, Viterbi decoder, low power, minimum transition traceback, high-radix ACS unit
相關次數：	點閱：2 下載：0
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當人們習慣於使用無線通訊產品，如手機、無線區域網路等，必須要克服通道雜訊所帶來的影響，因此使用通道編碼的技術。迴旋編碼器與菲特比解碼器常被廣泛地使用在現代的數位無線通訊系統中，以達成低位元錯誤率的資料傳輸。而隨著無線通訊的快速發展，對於大限制長度的迴旋編碼器，一個高速度、低功率、低成本的菲特比解碼器就相當的重要了。
在這本論文中，我們研究一個使用最少轉換的回溯技巧，並且提出一個方法來實現低功率的菲特比解碼器。我們結合最少轉換的回溯技巧與使用高基底的加法比較選擇運算單元，使得在處理回溯運算時，讀取記憶體的次數可以大幅的減少。另外由於使用高基底的加法比較選擇運算單元，因此在實現硬體方面，為了維持相同的資料傳輸速度，我們也可以使用較低速度的電路時脈。由於較少的記憶體讀取次數與較低的電路時脈，在功率消耗方面可以大幅的減低，以達成一個低功率的菲特比解碼器。
我們實現兩個使用不同基底之加法比較選擇運算單元的菲特比解碼器，實驗結果證實我們所提出的方法確實可行。使用較高基底之加法比較選擇運算單元的菲特比解碼器，對於功率的消耗上至少都有超過20%的改進。而在我們的實驗中，我們使用的是IEEE 802.16a的菲特比解碼器。

Convolutional encoder and Viterbi decoder are widely used in modern digital wireless communication system to achieve low bit-error-rate data transmission. Rapid developments in wireless communication have created a rising demand for high-speed, low-power, and low cost Viterbi decoder for large constraint length convolutional codes. In this thesis, we investigate the minimum transition traceback scheme and propose a scheme for the implementation of a low-power Viterbi decoder. We combine the minimum transition traceback scheme with the high-radix ACS (Add-Compare-Select) functional unit, the count of memory accesses needed to perform the traceback function can sufficiently be reduced. Therefore, the power consumption can also be reduced. Experimental results are presented to confirm the efficiency of the proposed scheme. In experiments, the Viterbi decoder for the IEEE 802.16a WMAN receiver was used.

Abstract ……………………………………………………………… 01
Contents ……………………………………………………………… 02
List of Figures ……………………………………………………… 04
List of Tables ………………………………………………………… 06
Chapter 1 Introduction …………………………………………… 07
1.1 Motivation ……………………………………………………… 09
1.2 Thesis Organization …………………………………………… 09
Chapter 2 Overview of Viterbi Decoder ………………………… 10
2.1 Convolutional Encoder ………………………………………… 10
2.2 Viterbi Algorithm ……………………………………………… 14
2.3 Architecture of Viterbi Decoder ……………………………… 18
Chapter 3 Low-Power Methodology ……………………………… 20
3.1 Minimum Transition Traceback Scheme ……………………… 20
3.2 Our Low-Power Scheme ……………………………………… 23
Chapter 4 Simulation Environment and Implementation ……… 28
4.1 Simulation Environment ……………………………………… 28
4.1.1 Our Simulation Environment …………………………… 29
4.1.2 Convolutional Encoder ………………………………… 29
4.1.3 Puncture and Depuncture ……………………………… 30
4.1.4 Mapping and Demapping ……………………………… 31
4.1.5 AWGN Channel ………………………………………… 32
4.1.6 Viterbi Decoder ………………………………………… 32
4.2 Implementation ………………………………………………… 33
4.2.1 Design Flow ……………………………………………… 34
4.2.2 Chip Implementation …………………………………… 35
4.2.3 FPGA Prototyping Verification ………………………… 38
Chapter 5 Experimental Results ………………………………… 40
5.1 Bit-Error-Rate ………………………………………………… 40
5.2 Memory Accesses ……………………………………………… 42
5.3 Power Analysis ………………………………………………… 46
Chapter 6 Conclusion ……………………………………………… 49
Bibliography ………………………………………………………… 50

                                

[1] IEEE Std. 802.16aTM-2003 Wireless MAN, Air Interface for Fixed Broadband Wireless Access Systems: Medium Access Control (MAC) Modifications and Additional Physical Layer Specifications for 2-11 GHz.
[2] J. G. Baek, S. H. Yoon, and J. W. Chong, “Memory efficient pipelined Viterbi decoder with look-ahead trace back”, IEEE International Conference on Electronics, Circuits and Systems (ICECS), Volume 2, pp. 769-772, September 2001.
[3] Y. N. Chang, H. Suzuki, and K. K. Parhi, “A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder”, IEEE Journal of Solid-State Circuits, Volume 35, Issue 6, pp. 826-834, June 2000.
[4] S. H. Choi, and J. J. Kong, “State parallel Viterbi decoder soft IP and its applications”, IEEE International Conference on Electrical and Electronic Technology, Volume 1, pp. 355-358, August 2001.
[5] T. Conway, “Implementation of high speed Viterbi detectors”, Electronics Letters, Volume 35, Issue 24, pp. 2089-2090, November 1999.
[6] D. A. El-Dib, and M. I. Elmasry, “Modified register-exchange Viterbi decoder for low-power wireless communications”, IEEE Transactions on Circuits and Systems, Volume 51, Issue 2, pp. 371-378, February 2004.
[7] F. Ghanipour, and A. R. Nabavi, “Design of a low-power Viterbi decoder for wireless communications”, IEEE International Conference on Electronics, Circuits and Systems (ICECS), Volume 1, pp. 304-307, December 2003.
[8] M. Ghoneima, K. Sharaf, H. F. Ragai, and A. Ei-Halim Zekry, “Low power units for the Viterbi decoder”, Midwest Symposium on Circuits and Systems, Volume 1, pp. 412-415, August 2000.
[9] S. Haykin, “Communication systems”, Wiley, 2001.
[10] J. Heller, and I. Jacobs, “Viterbi Decoding for Satellite and Space Communication”, IEEE Transactions on Communications, Volume 19, Issue 5, pp. 835-848, October 1971.
[11] W. S. Ju, M. D. Shieh, and M. H. Sheu, “A Low-Power VLSI Architecture for the Viterbi Decoder”, Midwest Symposium on Circuits and Systems, Volume 2, pp. 1201-1204, August 1997.
[12] C. C. Lin, C. C. Wu, and C. Y. Lee, “A low power and high speed Viterbi decoder chip for WLAN applications”, European Solid-State Circuits Conference, pp. 723-726, September 2003.
[13] S. Lin, and D. J. Costello, “Error Control Coding: Fundamentals and Applications”, Prentice-Hall, 1983.
[14] X. Liu, and M. C. Papaefthymiou, “Design of a 20-mb/s 256-state Viterbi decoder”, IEEE Transactions on VLSI Systems, Volume 11, Issue 6, pp. 965-975, December 2003.
[15] Dae-Il Oh, and S. Y. Hwang, “Design of a Viterbi decoder with low power using minimum-transition traceback scheme”, Electronics Letters, Volume 32, Issue 24, pp. 2198-2199, November 1996.
[16] J. Proakis, “Digital Communications”, McGraw-Hill, 2000.
[17] L. Qiao, Y. Yuxin, W. Jinxiang, and Y. Yizheng, “VLSI implementation of a high-speed and low-power punctured Viterbi decoder”, IEEE Conference on Computers, Communications, Control and Power Engineering, Volume 2, pp. 1205-1208, October 2002.
[18] S. Ranpara, and D. S. Ha, “A low-power Viterbi decoder design for wireless communications applications”, IEEE International ASIC/SOC Conference, pp. 377-381, September 1999.
[19] J. H. Ryu, S. C. Kim, J. D. Cho, H. W. Park, and Y. H. Chang, “A new lower power Viterbi decoder architecture with glitch reduction”, IEEE Asia Pacific Conference on ASICs (AP-ASIC), pp. 83-86, August 1999.
[20] J. H. Ryu, S. C. Kim, J. D. Cho, H. W. Park, and Y. H. Chang, “Lower power Viterbi decoder architecture with a new clock-gating trace-back unit”, International Conference on VLSI and CAD (ICVC), pp. 297-300 October 1999.
[21] P. K. Singh, and S. Jayasimha, “A low-complexity, reduced-power Viterbi Algorithm”, International Conference on VLSI Design, pp. 61-66, January 1999.
[22] M. Traber, “A low power survivor memory unit for sequential Viterbi Decoders”, IEEE International Symposium on Circuits and Systems (ISCAS), Volume 4, pp. 214-217, May 2001.
[23] C. Y. Tsui, R. S. K. Cheng, and C. Ling, “Low power ACS unit design for the Viterbi decoder [CDMA wireless systems]”, IEEE International Symposium on Circuits and Systems (ISCAS), Volume 1, pp. 137-140, May 1999.
[24] K. Tsukano, T. Nishiya, T. Hirai, and T. Nara, “Simplified EEPR Viterbi detector based on a transformed radix-4 trellis for a disk drive”, IEEE Transactions on Magnetics, Volume 35, Issue 5, pp. 4387-4401, September 1999.
[25] C. W. Wang, and Y. N. Chang, “Design of Viterbi decoders with in-place state metric update and hybrid traceback processing”, IEEE Workshop on Signal Processing Systems, pp. 5-15, September 2001.

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