研究生: |
姜彥寧 Chiang, Yen-Ning |
---|---|
論文名稱: |
應用於非揮發性記憶體具臨界電壓補償架構之小偏移電流鏡 A Small Offset Current Mirror with Threshold-Voltage Compensation Scheme for Non-volatile Memories |
指導教授: |
張孟凡
Chang, Meng-Fan |
口試委員: |
邱瀝毅
Chiou, Lih-Yih 洪浩喬 Hong, Hao-Chiao |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering |
論文出版年: | 2017 |
畢業學年度: | 106 |
語文別: | 英文 |
論文頁數: | 73 |
中文關鍵詞: | 電流鏡 、臨界電壓補償 、非揮發性記憶體 |
外文關鍵詞: | current mirror, threshold voltage compensation, non-volatile memory |
相關次數: | 點閱:2 下載:0 |
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近年來,非揮發性記憶體相當普及並且應用極廣,也增加了高速度、低能量消耗、低成本元件的需求。伴隨著製程微縮與科技的進步,上個世代的主流非揮發性記憶體-快閃記憶體,遇到了低儲存單元電流、高臨界電壓飄移與耦合雜訊干擾等等的問題。許多新世代的非揮發興記憶體擁有潛力可以解決這些問題。而接觸點電阻式記憶體(Contact ReRAM)具有低寫入功耗、快速寫入時間、以及具有邏輯製成相容性,這些特性對產業界而言,極具吸引力與競爭力。然而,接觸點電阻式記憶體有著小阻值率(高阻值/低阻值)以及阻值高偏移問題,使得讀取增加許多困難。
我們提出具臨界電壓補償架構之小偏移參考電流產生器,來增加感測放大器輸入端的電壓差距。在輸入電壓由10uA至60uA的範圍,透過臨界電壓補償架構,我們可以使電流偏移量縮小了2.8倍至4.2倍,且無須耗費多於的讀取時間。此外,在位元線長度為512時,相比於開啟4顆參考細胞並使用傳統電流鏡,我們提出的小偏移電流鏡可以加速讀取1.17倍,相比於開啟1顆參考細胞,我們的架構可以加速讀取1.54x。
我們在1Mb 電阻式隨機存取記憶體實現我們的小偏移參考電流產生器,此專案於台積電65奈米標準CMOS製程下製作。藉由我們的小偏移參考電流產生器,在位元線長度為512時,量測電阻式隨機存取記憶體之讀取時間可以達到3.0ns。
Recently, non-volatile memory (NVM) is popular and used in many applications, which requirements for higher performance, lower power and low cost. However, as technology shrinks, flash memories, the mainstream of NVM in last century, face the challenges, such as small cell current, large variation of threshold voltage and coupling noise. Many emerging non-volatile memories have great potential to overcome those problems and to replace the flash memory. CRRAM features low write voltage, short program time and logic-process compatibility, and make CRRAM attractive to industry. However, small R-Ratio (RHRS/RLRS) and variation of resistance lead to the difficulties in read.
We proposed a small offset reference generator with Threshold-Voltage Compensation Scheme by enlarging the difference of input current in sense amplifier. The offset suppression is about 2.8x~4.2x smaller across 10uA to 60uA of input current by our threshold voltage compensated scheme, which with zero timing overhead in read operation. In addition, we can achieve 1.17x faster speed than the conventional CM with 4 activated replica cells and can achieve 1.54x than with 1 activated replica cell at BL-Length=512.
We implement our proposed small offset reference generator into a 1Mb ReRAM macro fabricated in TSMC 65nm CMOS process. The measured read access time can achieve3.0ns by our proposed scheme at BL-Length=512.
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