為了持續改善元件的性能，金氧半元件之閘極氧化層(SiO2) 的厚度必須繼續縮小，然而極薄的閘極氧化層常伴隨著高的閘極漏電流，為了減少閘極漏電流，high-k材料已被廣泛使用來取代二氧化矽作為金氧半元件的閘極介電層。然而，high-k材料仍面臨一些技術性的挑戰例如像電荷捕捉和遷移率惡化…等問題。所以為了克服這些因素才有了介面處理，以及通道利用可以提供較高遷移率的含鍺半導體材料，因為純鍺本身對矽而言，載子遷移率電子提升兩倍至於電洞可以提升四倍，對於元件傳輸可以大大得到改善。但是由於鍺的不耐高溫在400℃下產生易揮發的氣體且容易水解，對於元件的電特性會變差，所以勢必要用其它鈍化方式來抑制鍺擴散並且維持含鍺通道元件的電特性。
本論文首先透過二次離子質譜儀(Secondary Ion Mass Spectrometer, SIMS)來分析雜質擴散現象，結果發現可靠度SILC和Stress CV方面表現出較佳特性的MOS元件，SIMS分析後的觀察到Ge擴散程度也最小。而在PIII氮化Ta及TaN閘極結構發現，隨著PIII氮化相同閘極結構下的能量增大，其Hf-N的分佈差異不大。而在不同閘極(Ta 、TaN Gate)固定能量下PIII氮化，TaN Gate的Hf-N分佈都比Ta Gate的深， 這代表我們TaN Gate的N會因為PIII氮化時而往high-K擴散。
而第二部份的(a)、(b)實驗皆以後續PMA550℃為前提下探討最佳鍺磊晶厚度與Si-cap厚度，以利我們未來製作純鍺MOSFET以活化S/D溫度為550℃下的參考磊晶厚度。在純鍺磊晶厚度方面，越薄的鍺磊晶厚度有較佳的電特性，故未來在鍺厚度方面會以較薄的鍺磊晶當作考量。而在Si-cap厚度方面，雖然最厚的Si-cap=40Å厚度下有較好佳的特性，但是較厚的矽覆蓋厚度反而會降低在相同偏壓下對通道載子的控制能力，也就是元件的轉移電導(transconductance)會下降。因此希望Si-cap厚度能越薄越好，當矽覆蓋層厚度降為Si-cap=30Å時，其偏壓從空乏到累積區時電容值下降有些嚴重。所以我們元件在此退火前提下還是需要厚度40Å以上的矽覆蓋層，才足以阻擋鍺的擴散防止其影響元件特性。而在(c)實驗為改變不同矽鍺基板摻雜濃度，摻雜後其偏壓從空乏區到累積區時電容值下降的非常嚴重。矽鍺基板摻雜濃度在C-V以及I-V關係圖仍可發現一致性，也就是隨著摻雜濃度上升，其電容值的下降會越明顯且漏電流會越大。
由於高濃度矽化鍺無法結晶，所以論文最後探討鍺結晶的問題，結果發現純鍺虛擬基板覆蓋不同TEOS cap厚度後直接退火的結晶法效果不佳。超晶格結構不同純鍺磊晶厚度退火，其中較厚的鍺磊晶層結構XRD圖看出有不錯的鍺結晶效果，在粗糙度方面經過700℃退火後，其表面粗糙度皆有得到改善，但經過900℃退火粗糙度卻都比700℃退火後的來的差，推測是由於strained Ge轉換成relaxed Ge造成的線差排(threading dislocation)導致表面粗糙度的增生。

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