In this work, 4H-SiC lateral double RESURF MOSFETs on a semi-insulating substrate are fabricated. With the double RESURF structure , the depletion region can expand from both the upper side and the lower side of the drift region simultaneously, which makes the dose of the drift region twice that of single RESURF structure without degrading the breakdown voltage. Therefore, the drift region resistance can be reduced by half. And by using the HPSI substrate, the charge compensation can be easily controlled without the substrate-assisted-depletion effect, and the vertical breakdown by the epi thickness is no longer a limitation.
However, in the experiment, because the N drift region is too heavily doped and can not be completely depleted before the gate oxide breaks down. This causes the premature breakdown of the devices and the maximum drain voltage is only about 100V. In the forward conduction, the concentration of the p-type body is too high and which causes a high threshold voltage and the high channel resistance. The best achieved specific on-resistance is 162 mΩ-cm2 with 3 μm channel length and 20 μm drift region length when the electric field in the gate oxide is limited to 3 MV/cm.

本篇論文重點為在半絕緣基板上製作4H-SiC橫向高電壓double RESURF金氧半場效電晶體。在double RESURF結構下，空乏區可同時在漂移區外部及內部展開，這代表在漂移區內的摻雜劑量可提高到single RESURF結構的兩倍而不至於降低崩潰電壓，因此導通電阻可大幅地降低。而將元件製作在高純度半絕緣基板上，一方面可防止基板協助空乏效應的發生，使電荷平衡變得容易控制；另一方面，垂直方向的崩潰電壓將不再受到磊晶層厚度的限制。
然而，在本次實驗中，過高的漂移區濃度使漂移區無法在閘極氧化層崩潰前被完全空乏，使元件提前崩潰在汲極電壓約100伏特左右。在正向導通特性方面，因採用較高濃度的磊晶層，導致元件擁有較高的臨界電壓與通道電阻。量測到最佳導通電阻為162 mΩ-cm2，發生在通道長度3 μm 、漂移區長度20 μm的元件上，在閘極氧化層電場限制在3 MV/cm。

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