研究生: |
吳維軒 Wu, Wei-Hsuan |
---|---|
論文名稱: |
適用於LDPC編碼多天線系統的疊代式接收器 Design and Implememtation of an Iterative Detection and Decoding Receiver for LDPC coded MIMO Systems |
指導教授: |
翁詠祿
Ueng, Yeog-Luh |
口試委員: |
楊家驤
Yang, Chia-Hsiang 謝欣霖 Shieh, Shin-Lin |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
論文出版年: | 2013 |
畢業學年度: | 102 |
語文別: | 英文 |
論文頁數: | 66 |
中文關鍵詞: | 疊代式檢測以及解碼 、軟式輸入以及軟式輸出的多天線系統檢測器 、低密度奇偶校驗檢查碼 |
外文關鍵詞: | Iterative detection and decoding, Soft-input soft-output MIMO detector, Low-Decsity Parity-Check codes |
相關次數: | 點閱:2 下載:0 |
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據了解,低密度奇偶校驗編碼的多輸入多輸出系統的疊代檢測和解碼可以實現近容量的性能。
本文提出了第一個真正的高速,面積高效的疊代式檢測以及解碼器,
其中包含了一個最小均方誤差平行干擾消除的多天線檢測器和一個最小和低密度奇偶校驗檢查碼解碼器。
本文提出層狀非重設疊代檢測和解碼器可以用來增加收斂速度和降低疊代次數。
本文提出一個面積高效的最小均方誤差平行干擾消除的多天線檢測器設計,其中用QR分解來計算簡化反矩陣。
本文提出一個面積高效且有效地交換軟信息檢測器和解碼器之間的接口。
鑑於吞吐量的限制,內疊代和外疊代被合理地結合並達到其符合的性能。
藉由實現以上所提的技術,本論文實現了一個802.11n的一種規格的多輸入多輸出系統的疊代檢測和解碼器。
此接收器以40奈米製程所製造,998k 邏輯閘門而其面積為1.33平方毫米,最高工作頻率
是303兆赫,418 Mb / s的吞吐量在4乘4多天線系統以及16-QAM的配置。
該芯片的功耗為115 mW,在0.9 伏特的電壓供應下,實現能源效率275 PJ/bit。
相較於傳統的由現有的多天線檢測器以及低密度奇偶校驗檢查碼解碼器所組成的非疊代式接收器,
本設計達到了較好的面積和能量效率以及較好的性能。
It is known that low-density parity-check (LDPC)-coded multiple-input
multiple-output (MIMO) systems with iterative detection and decoding (IDD)
can achieve near-capacity performance. This paper presents the rst true high-
throughput, area-ecient IDD receiver, where an MMSE-PIC-based MIMO
detector and a min-sum-based LDPC decoder are embedded. A layered non-
resetting IDD scheduling is used to increase the error convergence rate and
to minimize the number of inner iterations. An area-ecient minimum mean-
square with error-parallel interference cancellation (MMSE-PIC) detector is
devised to simplify the computationally intensive matrix inversion by leverag-
ing QR decomposition. A detector-decoder interface with ecient scheduling is
proposed to exchange soft messages between the detector and decoder. Given
the throughput specication, inner and outer loops are optimally combined
to maximize the error performance. As the proof of concept, the proposed
IDD receiver is implemented for the IEEE 802.11n standard. Fabricated in
a 40nm CMOS process, the IDD receiver integrates 998k logic gates in 1.33
mm2. The maximum operating frequency is 303 MHz, achieving a through-
put of 418 Mb/s for a 44 16-QAM conguration. The chip dissipates 115
mW at 0.9 V, achieving an energy eciency of 275 pJ/bit. Compared to the
conventional non-iterative receivers, composed of state-of-the-art MIMO de-
tectors and LDPC decoders, this work achieves even higher area and energy
eciencies despite the improved error performance.
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