簡易檢索 / 詳目顯示

研究生: 張宜菁
Chang, Yi-Ching
論文名稱: 低溫複晶矽薄膜電晶體中汲極漏電流抑制方法之研究
Study of Drain Leakage Current Suppression Method for LTPS TFTs
指導教授: 金雅琴
King, Ya-Chin
林崇榮
Lin, Chrong-Jung
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2010
畢業學年度: 98
語文別: 中文
論文頁數: 69
中文關鍵詞: 低溫複晶矽薄膜電晶體汲極漏電流
外文關鍵詞: Low-temperature polycrystalline-silicon (LTPS), Thin-film-transistor (TFT), Drain leakage current
相關次數: 點閱:2下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • LTPS-TFTs元件,由於晶粒邊界與晶粒內之缺陷以及其較陡的汲極端接面,使其關閉時的漏電流特性與一般的MOSFETs元件不同。為了分析LTPS-TFTs元件之漏電特性,我們利用製程模擬軟體定義出元件的二維架構,再而藉由電性模擬軟體讀取經由其建構完成的元件架構,了解漏電之成因,進而提出藉由熱電洞注入降低汲極端電場的方法。論文中並模擬討論在不同量的熱電洞及儲存位置對漏電流特性之影響。在實驗方面,本論文探討熱電洞注入效應對元件的影響,利用能帶間熱電洞的注入效應,改善閘極引發汲極漏電流(Gate-induced-drain-leakage current, GIDL),增加低溫複晶矽薄膜電晶體的開關電流比,且針對修復速度、可靠度做詳細的分析及討論,達到優越的元件特性。


    LTPS-TFTs, due to the high density defects located at the grain boundary and the in-grain as well as sharper drain junction, exhibit unique off-sate leakage current characteristics. The two-dimensional process simulator was adopted for constructing the poly-Si TFT structure, and then electric characteristics of the device were then evaluated by the 2D-device simulator. In this simulation, it was found that by introducing hot holes in the dielectric film, GIDL can be effectively suppressed. Through a series of simulations, the amount as well as the location of the position charge stored in the dielectric layer for the best suppression effect is analyzed. Based on the experimental results, the GIDL current can be significantly suppressed after band-to-band hot hole (BBHH) stress. This stress method is able to increase the on/off ratio of the LTPS-TFTs. Finally, the speed of hot hole injected and the stability of the suppression effect is investigated.

    摘要 i ABSTRACT ii 致謝 iii 內文目錄 iv 附圖目錄 vi 表格目錄 x 第一章序論 1 1.1研究動機 1 1.2章節介紹 2 第二章低溫複晶矽薄膜電晶體汲極漏電流之特性回顧 3 2.1 元件結構對於汲極漏電流的影響 3 2.1.1 Offset-Gate TFT結構 3 2.1.2 Gate-Overlapped LDD TFT結構 4 2.1.3 Self-Aligned FID TFT結構 5 2.2 Stress引發汲極漏電流的變化 5 2.2.1 閘極高電壓stress 5 2.2.2 汲極加閘極高電壓stress 6 2.3 汲極漏電流特性比較 7 第三章低溫複晶矽薄膜電晶體中汲極漏電流抑制方法 12 3.1 LTPS-TFTs製作流程與關閉電流來源分析 12 3.2 元件特性模擬 14 3.2.1 電洞注入位置 14 3.2.2 儲存於介電層之電洞對於元件特性的影響 15 3.2.3 電洞注入對汲極漏電流之影響 16 3.3 小結 16 第四章實驗量測結果與討論 31 4.1 電洞注入方式 31 4.1.1 Fowler-Nordheim (FN)穿隧 31 4.1.2 能帶間熱電洞注入機制 32 4.1.3 熱電洞注入效率 33 4.2 高溫活化汲極漏電流特性的影響 35 4.3 光漏電流特性的變化 35 4.4 電洞注入對元件特性之影響 36 4.5 小結 37 第五章總結 65 參考文獻 66

    [1]S.D. Brotherton, “Polystalline silicon thin film transistors,” Semicond. Sci. Technol., vol.10, NO.6, pp. 721-738, JUNE 1995.
    [2]T. Noma, T. Yonehara, H. Kumomi, “Crystal forms by solid‐state recrystallization of amorphous Si films on SiO2,” Appl. Phys. Lett., vol. 59, NO.6, pp. 653-655, 1991.
    [3]Seok-Woon Lee, Seung-Ki Joo, “Low temperature poly-Si thin-film transistor fabrication by metal-induced lateral crystallization,” IEEE Electron Device Lett., vol.17., NO.4., Aug. 2002, pp. 160 - 162.
    [4]Toshiyuki Sameshima, Masaki Hara and Setsuo Usui, “XeCl Excimer Laser Annealing Used to Fabricate Poly-Si TFT's,” Jpn. J. Appl. Phys. 28, 1989, pp. 1789-1793.
    [5]Sang-Hoon Jung, Woo-Jin Nam, and Min-Koo Han, “A new voltage-modulated AMOLED pixel design compensating for threshold voltage variation in poly-Si TFTs,” IEEE Electron Device Lett., vol.25., NO.10., Oct. 2004, pp. 690-692.
    [6]Jung-Hoon Oh, Hoon-Ju Chung, Nae-In Lee, and Chul-Hi Han, “A high-endurance low-temperature polysilicon thin-film transistor EEPROM cell,” IEEE Electron Device Lett.,vol.21.,NO.6.,JUNE 2000, pp. 304.
    [7]Kazuhiro Kobayashi, Hiroyuki Murai, Takao Sakamoto, Kris Baert, Hidetada Tokioka, Takashi Sugawara, Yuuichi Masutani, Hirofumi Namizaki and Masahiro Nunoshita, “A Novel Fabrication Method for Polycrystalline Silicon Thin-Film Transistors with a Self-Aligned Lightly Doped Drain Structure,” Jpn. J. Appl. Phys. 32, 1993, pp. 469-473.
    [8]Byung-Hyuk Min, Kanicki, J., “Electrical characteristics of new LDD poly-Si TFT structure tolerant to process misalignment,” IEEE Electron Device Lett., vol. 20, NO. 7., Jul 1999, pp. 335-337.
    [9]Yung-Chun Wu, Ting-Chang Chang, Po-Tsun Liu, Cheng-Wei Chou, Yuan-Chun Wu, Chun-Hao Tu, Chun-Yen Chang, “Reduction of leakage current in metal-induced lateral crystallization polysilicon TFTs with dual-gate and multiple nanowire channels,” IEEE Trans. Electron Devices, vol. 26, NO. 9, Setp. 2005, pp. 646-648.
    [10]Min-Cheol Lee, Min-Koo Han, “Poly-Si TFTs with asymmetric dual-gate for kink current reduction,” IEEE Electron Device Lett., vol. 25, NO. 1, Jan. 2004, pp. 25-27.
    [11]Byung-Hyuk Min, Cheol-Min Park, Min-Koo Han, “A novel offset gated polysilicon thin film transistor without an additional offset mask,” IEEE Electron Device Lett., vol. 16, NO. 5, May 1995, pp. 161-163.
    [12]Kwon-Young Choi, Min-Koo Han, “A novel gate-overlapped LDD poly-Si thin-film transistor,” IEEE Electron Device Lett., vol. 17, NO. 12, Dec 1996, pp. 566-568.
    [13]Horng-Chih Lin, Yu, C.-M., Lin, C.-Y., Yeh, K.-L., Tiao-Yuan Huang, Tan-Fu Lei, “A novel thin-film transistor with self-aligned field induced drain,” IEEE Electron Device Lett., vol. 22, NO. 1, Jan 2001, pp. 26-28.
    [14]Takabatake, M., Ohwada, J., Ono, Y.A., Ono, K., Mimura, A., Konishi, N., “CMOS circuits for peripheral circuit integrated poly-Si TFT LCD fabricated at low temperature below 600°C,” IEEE Trans. Electron Devices, vol. 38, NO. 6, Jun 1991, pp. 1303-1309.
    [15]Yukiharu Uraoka, Hiroshi Yano, Tomoaki Hatayama, Takashi Fuyuki, Masahiro Nunoshita, “Comprehensive Study on Reliability of Low-Temperature Poly-Si Thin-Film Transistors under Dynamic Complimentary Metal-Oxide Semiconductor Operations,” Jpn. J. Appl. Phys. 41, 2002, pp. 2414-2418.
    [16]Yukiharu Uraoka, Tomoaki Hatayama, Takashi Fuyuki, Tetsuya Kawamura, Yuji Tsuchihashi, “Reliability of High-Frequency Operation of Low-Temperature Polysilicon Thin Film Transistors under Dynamic Stress,” Jpn. J. Appl. Phys. 39, 2000, pp. L1209-L1212.
    [17]Kow Ming Chang, Yuan Hung Chung, Gin Ming Lin, “Anomalous variations of OFF-State leakage current in poly-Si TFT under static stress,” IEEE Electron Device Lett., vol. 23, NO. 5, May 2002, pp. 255-257.
    [18]Kohji Ohgata, Yasuyoshi Mishima, Nobuo Sasaki, “A new dopant activation technique for poly-Si TFTs with a self-aligned gate-overlapped LDD structure,” IEDM Tech. Dig., 2000, pp. 205-208.
    [19]T. Sameshima, S. Usui, and M. Sekiya, “XeCl excimer laser annealing used in the fabrication of poly-Si TFT’s,” IEEE Electron Device Letters., vol.EDL-7, No.5, 1986, pp. 276.
    [20]AS. Grove. In: “Physics and technology of semiconductor devices.”Wiley, New York, 1967.
    [21]Y. Kuo “Plasma enhanced chemical vapor deposited silicon nitride as a gate dielectric film for amorphous silicon thin film transistors—A critical review,” Vacuum, vol. 51, Dec. 1998, pp. 741.
    [22]Min-Koo Han, and In Hyuk Song, “Invited Paper: Low Temperature Poly-Si TFTs with Advanced Device Structures,” SID Symposium Digest of Technical Papers, vol. 34, no.1, May 2003, pp.1490-1493.
    [23]Chan, T.Y., Chen, J., Ko, P.K. , Hu, C., “The impact of gate-induced drain leakage current on MOSFET scaling,” IEEE Electron Device Lett., vol. 33, 1987, pp. 718-721.
    [24]Aaron Marmorstein and Apostolos T. Voutsas, “A Systematic Study and Optimization of Parameters Affecting Grain Size and Surface Roughness in Excimer Laser Annealed Polysilicon Thin Films,” J. Appl. Phys., Vol. 82, pp. 1, 1997.
    [25]M. Lenzlinger and E. H. Snow, “Fowler-Nordheim tunneling into thermally grown SiO2,” J. Appl. Phys., Vol. 40, No. 1, pp. 278-283, 1969.
    [26]Joe E. Brewer, Manzur Gill, “Nonvolatile memory technologies with emphasis on flash,” IEEE press, 2008, page:341-342.
    [27]Ayres, J.R., Brotherton, S.D., Clarence, I.R., Dobson, P.J., “Photocurrents in poly-Si TFTs,” IEE Proc.-Circuits, Devices Syst., vol. 141, NO. 1, Feb 1994, pp. 27-32.

    無法下載圖示 全文公開日期 本全文未授權公開 (校內網路)
    全文公開日期 本全文未授權公開 (校外網路)

    QR CODE