近年來，人工智慧領域隨著深度神經網路的快速發展已被廣泛實現於生活中的許多應用，隨著應用的複雜度提升，深度神經網路所需的參數量也越趨龐大。在蓄電量有限的邊緣裝置上執行推論時，龐大的參數量以及計算量會導致可觀的資料搬運能耗，限制了邊緣裝置的可工作時間。因此，如何減少資料搬運是一項重要的課題。
在本研究中，考慮深度神經網路具有每層網路參數不同以及輸入圖片大小不同的特性，提出了一個片上記憶體存取最佳化的方法以取得較佳的資料流進行運算，再透過調整運算陣列的資料復用比例，達到片上記憶體存取次數減少的目的。基於此演算法，本研究提出一個可重新配置之運算陣列，其採用輸出固定資料流，並具有省略數值為零的計算判斷機制，進一步降低推論所需的能耗。
為了使加速器操作在多種模式的運算皆有良好的表現，本研究提出了融合資料記憶體塊，使運算陣列在不同網路特性下皆能保持良好的使用率。基於以上提到的演算法以及硬體設計，使加速器可以達到1.93TOPS/W的能量效率。

In recent years, with the rapid development of deep neural networks in the field of artificial intelligence, it has been widely implemented in many applications in life. As the complexity of applications increases, the amount of parameters required by deep neural networks is also increasing. When performing inferences on edge devices with limited power storage, the vast amount of parameters and computation will lead to significant data handling energy consumption, limiting the available time of the edge devices. Therefore, how to reduce data handling is an important issue.
In this research, considering that the deep neural network has the characteristics of different network parameters of each layer and different input image sizes, an on-chip memory access optimization method is proposed to obtain a better data flow for operation. Based on this algorithm, this study proposes a reconfigurable processing element array, which uses an output stationary dataflow and has a zero-gatting mechanism that omits zero values, reducing the energy consumption required for inference. And then adjust the data multiplexing ratio of the arithmetic array to reduce the number of on-chip memory accesses. In order to make the accelerator operate well in various modes of operation, this study proposes a fused data memory banking scheme so that the computing array can maintain a high utilization rate under different network characteristics. Based on the algorithm mentioned above and hardware design, the accelerator can achieve an energy efficiency of 1.93TOPS/W.

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