在大部分的 DSP 應用中，Multiply-And-Accumulate (MAC) 是最常使用到的運算之一。我們提出了利用軟體的方法來自動產生高效能、可合成之 Verilog 硬體描述語言的 MAC 模組。這套軟體結合了多種新穎的技術，包括：radix-4 Booth encoding、three dimensional method、sign-extension prevention scheme 以及結合了 carry-select 和 carry-look-ahead 的加法器。除此之外，這套軟體還提供多種選項供使用者設定，包括：１､輸入與輸出訊號的位元寬度。２､輸入與輸出訊號的表示法（有號數、無號數或根據其他輸入訊號來決定）。３､多少級 pipeline。４､當發生 overflow 時，是否要改變結果。５､累加器的類型（只支援加法、或支援加法與減法）。６､pipeline stall 的功能。７､結果初始值的設定。一個常用的 MAC 模組（16x16 的輸入訊號、40-bit 的輸出結果、兩級 pipeline）可以在數秒內產生，而且工作頻率高達280 MHz（in post-layout simulation typical case when targeted toward a TSMC 0.35μm CMOS cell library）。
為了減少設計所需要的時間，設計一套軟體能夠自動產生使用者自訂的 MAC 模組，對於 DSP 積體電路的設計者而言，將是一大幫助。我們已經發展了一個 MAC 模組產生器，它提供了許多選項供使用者設定，讓使用者可以根據設計的需求來設定這些選項，產生所需要的 MAC 模組。

我們的 MAC 模組產生器可以產生四種不同的架構：三級管線、二級管線、一級管線以及組合性電路。一個 MAC 模組包含一個乘法器與一個加法器。乘法器是由 radix-4 Booth encoder、modified Wallace addition tree 以及 sign-extension prevention scheme 所組成。而加法器的組成則根據 MAC 模組的架構而有所不同。若 MAC 模組是三級管線或二級管線，則加法器是三個運算元的加法器；否則就是兩個運算元的加法器。

我們這套軟體最大的貢獻在於：根據不同的 MAC 模組架構，提出相對應的設計方法，以達到最高效能。

Multiply-And-Accumulate (MAC) is the most frequently used operation in many DSP applications. We propose a software method that can generate high-performance MAC units in synthesizable HDL format. Our tool integrates several novel techniques including a modified radix-4 Booth encoding, a three dimensional Wallace tree, a sign-extension prevention scheme , and a hybrid carry-select/carry-look-ahead adder. It allows users to specify the number of bits in both inputs and output, the number system (signed or unsigned or decided by command inputs), the number of pipeline stages, saturation option on overflow, accumulator type (“addition only” or “addition and subtraction”), and pipeline stall as well as accumulator initialization capability. A typical MAC unit (16x16 inputs, 40-bit Accumulation , 2-stage pipeline) can be generated within seconds and run at over 280 MHz in post-layout simulation typical case when targeted toward a TSMC 0.35μm CMOS cell library.

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