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研究生： 翟靖宇
Ching-Yu Chai
論文名稱： 高速骨牌電路設計自動化
Design Automation of High Speed Domino Circuits
指導教授： 張世杰
Shih-Chieh Chang
口試委員:
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年： 2007
畢業學年度： 95
語文別： 英文
論文頁數： 36
中文關鍵詞： 骨牌電路 、設計自動化
外文關鍵詞： domino circuit, design automation
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    • 一般來說骨牌電路具有較高操作速度的優點，因此被廣泛使用在許多高性能的電路中，例如CPU及DSP晶片。雖然骨牌電路較傳統的CMOS電路有較高的執行速度，然而，雖然相較於標準CMOS電路而言，骨牌電路有運算快速的特點，然而當今市面上卻沒有專為骨牌電路設計的電路合成軟體。因此，利用傳統的電路合成流程對骨牌電路進行合成，可能無法將骨牌電路高速運算的優點完全發揮。本篇論文以此為出發點，利用各種方法，使骨牌電路實作的電路速度加以提升。
    研究方向主要可以分成幾個部分，第一個部分利用修改電路的結構，將原始電路進行node(gate)合併的動作，再將合併後的結果和合成工具整合計算來達到提升速度的功能。第二個部分是利用output phase assignment將電路中並聯的邏輯閘比例提升，藉此增快骨牌電路骨牌電路的放電速度。第三部分是利用建立移除Domino cell的Foot NMOS模型，模擬並觀測Domino circuit在移除Foot NMOS後的速度提升。另外，本篇論文也針對Pin assignment進行研究，利用Pin assignment的方式來進行最後的優化，可惜未能在實驗中呈現出良好的效果，因此未列入我們最後的實驗結果中。
    這項研究和工業界合作，因此所使用到的各種軟硬體工具，都和當今標準的design flow整合，證明此項研究提出的方法確實可以應用在業界的設計當中。在實際效能改進的數據上，平均而言，我們的方法相對於傳統靜態0.13um製程的CMOS電路設計可提昇47.01%的電路效能。

    Domino logic is widely used in today's high performance circuit design. Although domino logic has high speed property than static CMOS logic, commercial tools do not support any special synthesis methods for domino logic. Therefore domino logic synthesis might not have good timing results when using traditional synthesis flow. In this paper, we have purposed following several methods: partially collapse, output phase assignment for timing improvement, remove foot NMOS, and pin assignment to improve circuit timing, but pin assignment does not have good results in our experiments, so we do not use in our final experiments. The other three methods presented here are combined with domino circuit traditional synthesis flow. Our works have better timing results of up to 47% than synthesizing circuits with 0.13um static CMOS library developed by Faraday Corporation.

    List of Contents: Abstract 1 Contents 2 List of Figures 3 List of Tables 4 Chapter 1 Introduction 5 Chapter 2Partially Collapse for Timing Optimization 10 Chapter 3 Output Phase Assignment for Timing Optimization 16 Chapter 4 Remove Foot NMOS for Timing Optimization 21 Chapter 5 Pin Assignment for Timing Optimization 26 Chapter 6 Overall Flow 29 Chapter 7 Experimental Results 31 Chapter 8 Conclusions 34 References 35 List of Figures: Fig. 1: A typical domino circuit 5 Fig. 2: Traditional domino synthesis flow 7 Fig. 3: The example of partially collapse for timing optimization 11 Fig. 4: The connection between each node and nodes in the t_slice list 13 Fig. 5: The final result of partially collapse nodes 14 Fig. 6: Different phase assignment for the same circuit 17 Fig. 7: Inverter trapped in the circuit 18 Fig. 8: Output phase assignment example 19 Fig. 9: The final result after performing output phase assignment 20 Fig. 10: 3-input domino AND cell 21 Fig. 11: DC current of the domino logic without foot NMOS 22 Fig. 12: The final result after performing output phase assignment 23 Fig. 13: The footless domino circuit with delay element 24 Fig. 14: Different pins have different speed 26 Fig. 15: The overall flow 29 List of Tables: Table 1: The final experimental results 32

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