高密度三維通孔電阻式隨機存取記憶體元件之研究

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研究生：	謝旻哲 Hsieh, Min-Che
論文名稱：	高密度三維通孔電阻式隨機存取記憶體元件之研究 Study of High-density 3D Via Resistive Random Access Memory in Nanoscale CMOS Technologies
指導教授：	金雅琴 King, Ya-Chin
口試委員:	侯拓宏 Hou, Tuo-Hung 葉鳳生 Yeh, Fon-Shan 張宗生 Chang, Tzong-Sheng 林泓均 Lin, Hong-Chin
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering
論文出版年：	2016
畢業學年度：	104
語文別：	英文
論文頁數：	137
中文關鍵詞：	互補式金氧半導體、非揮發性記憶體、後段製程、電阻式隨機存取記憶體
外文關鍵詞：	CMOS, NVM, BEOL, RRAM
相關次數：	點閱：2 下載：0
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隨著近年來互聯網相關應用以及手持式電子產品的蓬勃發展，對於內嵌於互補式金氧半導體(CMOS)積體電路之記憶體模組的需求亦是逐年增加。為了應付龐大的數位資訊處理與保存，具有高儲存密度、高可靠度的優勢並且能夠高速寫入/讀取的新興記憶體元件包括相轉式隨機存取記憶體(PCRAM)、磁阻式隨機存取記憶體(MRAM)以及電阻式隨機存取記憶體(RRAM)都具有成為下一世代下非揮發性記憶體(NVM)的潛力。本論文中首先將展示可完全相容於CMOS邏輯製程之鋁後段製程(BEOL)的新型高密度通孔電阻式隨機存取記憶體元件，此一元件可透過簡單的光罩設計製作，除了具備優秀的元件特性外，亦可透過後段製程的連續堆疊來生產三維度儲存陣列以實現超高密度儲存陣列。然而，隨著製程技術不斷微縮並發展至高介電係數金屬閘極(HKMG)互補式金氧半導體先進製程，其後段製程技術中的通孔製造方式從傳統使用的單鑲嵌式演進至雙鑲嵌式，且接點使用的金屬材質亦從銅鋁合金改成銅。此外，為了穩定三維度儲存陣列的操作特性，一個可搭配通孔電阻式隨機存取記憶體元件使用的選擇元件將可堆疊於記憶體元件之上來實現一二極體一電阻(1D1R)的交叉點式儲存陣列。最後，一種新型雙位元通孔電阻式隨機存取記憶體也將於本論文中討論。除了同樣採用先進銅製程進行製造之外，此一元件更具備雙位元儲存能力以及自我整流之特性。以上三種不同的通孔電阻式隨機存取記憶體元件皆具備微小的元件尺寸、容易製造、可三維堆疊、高速切換組態、高阻態比以及優異的可靠度特性等優點，將可望成為下一世代高密度非揮發性記憶體陣列的解決方案之一。

Due to the fast development of internet applications and handheld electronic products, demands of various memory modules in ultra-large scale integration (ULSI) circuits increase every year. For non-volatile data storage applications, emerging memories such as phase change random access memory (PCRAM), magetoresistive random access memory (MRAM) and resistive random access memory (RRAM) were investigated. These next-generation nonvolatile memories (NVM) have the advantages of high storage density, excellent reliability and high write/read speed.
In this dissertation, a new high-density via RRAM which is fully compatible with aluminum-based complimentary metal-oxide-silicon (CMOS) logic back-end-of-line (BEOL) process are proposed and studied first. This device can be easily implemented through special design in the single mask layer layout. This device exhibits excellent electrical characteristics and has the feature to achieve ultra-high storage density array in a repeatable pattern in standard BEOL layers.
As CMOS technologies push forward, the fabrication method of via in BEOL evolves from the traditional single-damascene method to dual-damascene method and the material of via also change from aluminum to copper. In addition, a back-end selector, which compatible with this copper-based via RRAM, is developed to be stacked above the via RRAM to achieve 1D1R cross-point memory array, making 3D-stackable memory array possible.
Finally, a novel twin-bit via RRAM is also demonstrated in this dissertation. The novel memory cell not only can be fabricated in advanced copper-based technology, but also enable the capacity of two bits storage and self-rectifying characteristic. These different via RRAMs all possess advantages such as small cell size, CMOS compatibility, 3D stacking ability, high switching speed, good reliability. Therefore, via RRAM is expected to become available solution for next-generation high-density NVM.

Abstract    i
摘要    iii
Acknowledgement    iv
Table of Contents    v
List of Tables    vii
List of Figures    viii
Chapter 1 Introduction    1
1 Preface    1
2 Challenges of Non-Volatile Memories    2
3 Motivation    3
4 Dissertation Organization    4
Chapter 2 Emerging Non-Volatile Memories    6
1 Introduction    6
2 Phase Change Random Access Memory (PCRAM)    7
3 Magnetoresistive Random Access Memory (MRAM)    8
4 Resistive Random Access Memory (RRAM)    10
4.1 Components and Materials    10
4.2 Operation Principles and Mechanisms    11
4.3 Driving Devices and Array Architectures    12
5 Summary    15
Chapter 3 3D Via Resistive Random Access Memory (Via RRAM) in Aluminum-based Process    24
1 Introduction    24
2 Development of Via RRAM in Aluminum-based BEOL Process    25
2.1 Single-damascene Process    26
2.2 Via sizing Effect    26
2.3 Fabrication in Aluminum Damascene Process    27
3 Characterization of Via RRAM in Aluminum Damascene Process    28
3.1 Switching Behaviors in Aluminum BEOL Process    28
3.2 Reliability in Aluminum Process    29
4 Summary    30
Chapter 4 3D Via Resistive Random Access Memory (Via RRAM) in Copper-based Process    47
1 Introduction    47
2 Development of Via RRAM in Copper-based BEOL Process    48
2.1 Dual-damascene Process    48
2.2 Fabrication in Copper Damascene Process    49
3 Characterization of Via RRAM in Copper Damascene Process    50
3.1 Switching Behaviors in Copper BEOL Process    51
3.2 Reliability in Copper Process    52
4 1D1R Ultra-high-density Cross-Point Array in Copper Damascene Process………….    52
4.1 Review of Selector in Cross-Point Array Applications    53
4.2 Characteristics of Via Diode in Copper Process    54
4.3 Operation Principles of 1D1R Memory Cell    55
5 Summary    57
Chapter 5 Twin-bit Via Resistive Random Access Memory (Twin-bit Via RRAM) in Copper-based Process    86
1 Introduction    86
2 Cell Structure and Fabrication    87
3 Characterization of Twin-bit Via RRAM in Copper Damascene Process    87
3.1 Switching Behaviors of Twin-bit Via RRAM    88
3.2 Reliability of Twin-bit Via RRAM    89
4 Twin-bit Via RRAM Array    90
4.1 Cross-Point Array    90
4.2 3D Interweaved Cross-Point Array    92
5 Summary    92
Chapter 6 Conclusion    117
1 Conclusion    117
Chapter 7 Future Work    121
1 Future Work    121
References    123
Vita    136

                                

Chapter 1

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Chapter 2

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Chapter 3

[1] Y. H. Tseng, C.-E. Huang, C. -H. Kuo, Y. -D. Chih, and C. J. Lin, “High Density and Ultra Small Cell Size of Contact ReRAM (CR-RAM) in 90nm CMOS Logic Technology and Circuits,” in Electron Devices Meeting (IEDM), 2009 IEEE International, Dec. 2009, pp. 5.6.1-5.6.4.
[2] C.-H. Wang, Y.-H. Tsai, K.-C. Lin, M.-F. Chang, Y.-C. King, and C. J. Lin, S.-S. Sheu, Y.-S. Chen, H.-Y. Lee, F. T. Chen, and M.-J. Tsai, “Three-dimensional 4F2 ReRAM Cell with CMOS Logic Compatible Process,” in Electron Devices Meeting (IEDM), 2010 IEEE International, Dec. 2010, pp. 29.6.1-29.6.4.
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Chapter 4

[1] A. Kawahara, R. Azuma, Y. Ikeda, K. Kawai, Y. Katoh, K. Tanabe, T. Nakamura, Y. Sumimoto, N. Yamada, N. Nakai, S. Sakamoto, Y. Hayakawa, K. Tsuji, S. Yoneda, A. Himeno, K. Origasa, K. Shimakawa, T. Takagi, T. Mikawa, and K. Aono, “An 8 Mb Multilayered Cross-point ReRAM Macro with 443 MB/s Write Throughput,” Solid-State Circuits, IEEE Journal of, vol. 48, no. 1, pp. 178-185, 2013.
[2] M. Son, J. Lee, J. Park, J. Shin, G. Choi, S. Jung, W. Lee, S. Kim, S. Park, and H. Hwang, “Excellent Selector Characteristics of Nanoscale VO2 for High-density Bipolar ReRAM Applications,” Electron Device Letters, IEEE, vol. 32, no. 11, pp. 1579–1581, 2011.
[3] J. W. Seo, S. J. Baik, S. J. Kang, Y. H. Hong, J. H. Yang, and K. S. Lim, “A ZnO Cross-bar Array Resistive Random Access Memory Stacked with Heterostructure Diodes for Eliminating the Sneak Current Effect,” Applied Physics Letters, vol. 98, no. 23, pp. 233505-1– 233505-3, 2011.
[4] J. J. Huang, Y. M. Tseng, C. W. Hsu, and T. H. Hou, “Bipolar Nonlinear Ni/TiO2/Ni Selector for 1S1R Crossbar Array Applications,” Electron Device Letters, IEEE, vol. 32, no. 10, pp. 1427–1429, 2011.
[5] X. A. Tran, B. Gao, J. F. Kang, X. Wu , L. Wu, Z. Fang, Z. R. Wang, K. L. Pey, Y. C. Yeo, A. Y. Du, M. Liu, B. Y. Nguyen, M. F. Li, and H. Y. Yu, “Self-rectifying and Forming-free Unipolar HfOx Based-high Performance RRAM Built by Fab-avaialbe Materials,” in Electron Devices Meeting (IEDM), 2011 IEEE International, Dec. 2011, pp.31.2.1-31.2.4.

Chapter 5

[1] C.-W. Hsu, C.-C. Wan, I.-T. Wang, M.-C. Chen, C.-L. Lo, Y.-J. Lee, W.-Y. Jang, C.-H. Lin, and T.-H. Hou, “3D Vertical TaOx/TiO2 RRAM with Over 103 Self-Rectifying Ratio and Sub-μA Operating Current,” in Electron Devices Meeting (IEDM), 2013 IEEE International, Dec. 2013, pp.10.4.1-10.4.4.

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